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| 型号： | IBM25PPC750CXEJQ2013T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件页数： | 13/44页 |
| 文件大小： | 416K |
| 代理商： | IBM25PPC750CXEJQ2013T |
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Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 12 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
4.4 60x Bus Input AC Specifications
Table 4-7 provides the 60x bus input AC timing specifications for the PowerPC 750CXe as defined in
Figure 4-3 provides the input timing diagram for the PowerPC 750CXe.
Num
Characteristic
1.8V Mode
2.5V Mode
Unit
Notes
Min
Max
Min
Max
10a
Address/Data/Transfer attribute inputs valid to SYSCLK (input
setup)
1.10
—
1.25
—
ns
2
10b
All other inputs valid to SYSCLK (input setup)
1.10
—
1.25
—
ns
3
10c
Mode select input setup to HRESET (QACK)8
—
8
—
tsysclk
4, 5, 7
10d
TS to SYSCLK (input setup)
1.30
—
1.40
—
ns
—
10e
DBWO to SYSCLK (input setup)
1.50
—
1.60
—
ns
—
11a
SYSCLK to inputs invalid (input hold)
0.5
—
0.3
—
ns
2
11b
HRESET to mode select input hold (QACK)0
—
0
—
ns
4, 7
Notes:
1. Input specifications are measured from the midpoint voltage (+0.9V) of the signal in question to the midpoint voltage of the rising edge of the input
SYSCLK. Input and output timings are measured at the pin (see Figure 4-3).
2. Address/Data Transfer Attribute inputs are composed of all bidirectional and input signals except those listed in Note 3.
3. All other signal inputs are composed of the following: TA, QACK, and ARTRY.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4-4 on page 13).
5. t
SYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design and characterization, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the
PLL relock time during the power-on reset sequence.
Figure 4-3. Input Timing Diagram
VM
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (+0.8V for SYSCLK, +0.9V for all other I/O)
10b
10a
11a
VM
10d
10e
(Note: The 1.8 and 2.5V modes assume the same input midpoint for timing.)
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