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| 型号： | IBM25PPC750CXEJQ4012T |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封装： | 27 X 27 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件页数： | 17/44页 |
| 文件大小： | 416K |
| 代理商： | IBM25PPC750CXEJQ4012T |
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Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 16 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
4.5.1 IEEE 1149.1 AC Timing Specifications
Table 4-9 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 4-7, Figure 4-8,
Figure 4-9, and Figure 4-10. The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST.
Figure 4-7 provides the JTAG clock input timing diagram.
Table 4-9. JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 4-2 on page 7 for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
TCK frequency of operation
0
25
MHz
1
TCK cycle time
40
—
ns
2
TCK clock pulse width measured at +1.1 V
15
—
ns
3
TCK rise and fall times
0
2
ns
4
Specification obsolete, intentionally omitted
5TRST assert time
25
—
ns
1
6
Boundary-scan input data setup time
0
—
ns
2
7
Boundary-scan input data hold time
13
—
ns
2
8
TCK to output data valid
–
8
ns
3, 5
9
TCK to output high impedance
3
19
ns
3, 4
10
TMS, TDI data setup time
0
—
ns
11
TMS, TDI data hold time
15
—
ns
12
TCK to TDO data valid
2.5
12
ns
5
13
TCK to TDO high impedance
3
9
ns
4
14
TCK to output data invalid (output hold)
0
–
ns
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
Figure 4-7. JTAG Clock Input Timing Diagram
1
2
3
VM = Midpoint Voltage (+0.9 V)
VM
TCK
VM
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