- 您现在的位置：买卖IC网 > PDF目录296203 > IC42S81600L-6T(G) 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM PDF资料下载
参数资料
| 型号： | IC42S81600L-6T(G) |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4银行（128 - Mbit的）同步动态RAM |
| 文件页数： | 8/69页 |
| 文件大小： | 1118K |
| 代理商： | IC42S81600L-6T(G) |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
16
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
Initiallization
Before starting normal operation, the following power on
sequence is necessary to prevent SDRAM from damged
or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE
high , DQN high and NOP condition at the inputs.
2. Maintain stable power, table clock , and NOP input
conditions for a minimum of 200us.
3. Issue precharge commands for all bank. (PRE or
PALL)
4. After all banks become idle state (after tRP), issue 8 or
more auto-refresh commands.
5. Issue a mode register set command to initialize the
mode regiser.
After these sequence, the SDRAM is in idle state and
ready for normal operation.
Programming the Mode Register
The mode register is programmed by the mode register
set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed
or the device loses power.
The mode register has four fields;
Options : A13 through A7
CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can
be asserted befor at least two clock cycles have elapsed.
CAS
CAS Latency
CAS latency is the most critical parameter being set. It
tells the device how many clocks must elapse before the
data will be available.
The value is determined by the frequency of the clock and
the speed grade of the device. The value can be pro-
grammed as 2 or 3.
Burst Length
Burst Length is the number of words that will be output or
input in read or write cycle. After a read burst is completed,
the output bus will become high impedance.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data
will be addressed. The order is programmable as either
“Sequential” or “Interleave”. The method chosen will
depend on the type of CPU in the system.
相关PDF资料 |
PDF描述 |
|---|---|
| IC42S81600L-6TG | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-6TI | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-6TIG | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7T | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7TG | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IC42S81600L-6TI | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-6TI(G) | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-6TIG | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7T(G) | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
发布紧急采购，3分钟左右您将得到回复。