- 您现在的位置：买卖IC网 > PDF目录296203 > IC42S81600L-7TI 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM PDF资料下载
参数资料
| 型号： | IC42S81600L-7TI |
| 英文描述： | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4（2）M中的x 8（16）位× 4银行（128 - Mbit的）同步动态RAM |
| 文件页数： | 13/69页 |
| 文件大小： | 1118K |
| 代理商： | IC42S81600L-7TI |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
IC42S81600/IC42S81600L
IC42S16800/IC42S16800L
20
Integrated Circuit Solution Inc.
DR023-0E 6/11/2004
Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters
the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as
follows.
P
rechargeE
Burst lengh=4
CLK
Command
CAS
latency = 2
DQ
Command
CAS
latency = 3
DQ
(tRAS is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
T0
T1
T2
T3
T4
T5
T6
T7
PRE
Hi - Z
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL(min.)
specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be
calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS
CAS latency
Read
Write
2-1
+ tDPL((min.)
3-2
+ tDPL((min.)
相关PDF资料 |
PDF描述 |
|---|---|
| IC42S81600L-8T | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TG | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TI | 4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC752CMO201 | INTERCONNECTION DEVICE |
| ICA-422-JGT | DIP22, IC SOCKET |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IC42S81600L-7TI(G) | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-7TIG | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8T | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8T(G) | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S81600L-8TG | 制造商:ICSI 制造商全称:Integrated Circuit Solution Inc 功能描述:4(2)M x 8(16) Bits x 4 Banks (128-MBIT) SYNCHRONOUS DYNAMIC RAM |
发布紧急采购，3分钟左右您将得到回复。