参数资料
型号: ICL7126CPL
厂商: Intersil
文件页数: 2/15页
文件大小: 0K
描述: IC ADC 3.5 DIGIT LCD LP 40-DIP
标准包装: 9
显示器类型: LCD
配置: 7 段显示
数字或字符: A/D,3.5 位数字
电流 - 电源: 70µA
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-DIP
包装: 管件
其它名称: ICL7126CPLIS
ICL7126
Absolute Maximum Ratings
Thermal Information
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V
Thermal Resistance (Typical, Note 2)
θ JA ( o C/W)
Analog Input Voltage (Either Input) (Note 1) . . . . . . . . . . . . .V+ to V-
Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . .V+ to V-
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEST to V+
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o C to 70 o C
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 o C
Maximum Storage Temperature Range . . . . . . . . . . -65 o C to 150 o C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 o C
NOTE: Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltages provided the input current is limited to ± 100 μ A.
2. θ JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
T A = 25 o C, V REF = 100mV, f CLOCK = 48kHz (Notes 1, 3)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM PERFORMANCE
Zero Input Reading
V IN = 0.0V, Full Scale = 200mV
-000.0
± 000.0
+000.0
Digital
Reading
Ratiometric Reading
V lN = V REF , V REF = 100mV
999
999/100
1000
Digital
0
Reading
Rollover Error
-V IN = +V lN ? 200mV
-
± 0.2
± 1
Counts
Difference in Reading for Equal Positive and Negative
Inputs Near Full Scale
Linearity
Full Scale = 200mV or Full Scale = 2V Maximum Deviation
-
± 0.2
± 1
Counts
from Best Straight Line Fit (Note 5)
Common Mode Rejection Ratio
Noise
V CM = ± 1V, V IN = 0V, Full Scale = 200mV (Note 5)
V IN = 0V, Full Scale = 200mV
-
-
50
15
-
-
μ V/V
μ V
(Peak-To-Peak Value Not Exceeded 95% of Time) (Note 5)
Leakage Current Input
Zero Reading Drift
Scale Factor Temperature Coefficient
V+ Supply Current
COMMON Pin Analog Common Voltage
V lN = 0V (Note 5)
V lN = 0V, 0 oC To 70 o C (Note 5)
V IN = 199mV, 0 oC To 70 o C ,
(Ext. Ref. 0ppm/× o C) (Note 5)
V IN = 0V (Does Not Include COMMON Current)
25k ? Between Common and Positive Supply
-
-
-
-
2.4
1
0.2
1
70
3.0
10
1
5
100
3.2
pA
μ V/ o C
ppm/ o C
μ A
V
(With Respect to + Supply)
Temperature Coefficient of Analog Common
25k ? Between Common and Positive Supply
-
80
-
ppm/ o C
(With Respect to + Supply) (Note 5)
Peak-To-Peak Segment Drive Voltage
V+ = to V- = 9V (Note 4)
4
5.5
6
V
Peak-To-Peak Backplane Drive Voltage
Power Dissipation Capacitance
vs Clock Frequency
-
40
-
pF
NOTES:
3. Unless otherwise noted, specifications are tested using the circuit of Figure 1.
4. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV.
5. Not tested, guaranteed by design.
2
FN3084.5
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