参数资料
型号: ICL7126CPLZ
厂商: Intersil
文件页数: 5/15页
文件大小: 0K
描述: IC ADC 3.5DIGIT LCD LP 40DIP
标准包装: 9
显示器类型: LCD
配置: 7 段显示
数字或字符: A/D,3.5 位数字
电流 - 电源: 70µA
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 40-DIP(0.600",15.24mm)
供应商设备封装: 40-DIP
包装: 管件
产品目录页面: 1236 (CN2011-ZH PDF)
ICL7126
Design Information Summary Sheet
V IN
I INT
V INT
C INT
? OSCILLATOR FREQUENCY
f OSC = 0.45/RC
C OSC > 50pF; R OSC > 50k ?
f OSC (Typ) = 48kHz
? OSCILLATOR PERIOD
t OSC = RC/0.45
? INTEGRATION CLOCK FREQUENCY
f CLOCK = f OSC /4
? INTEGRATION PERIOD
t INT = 1000 x (4/f OSC )
? 60/50Hz REJECTION CRITERION
t INT /t 60Hz or t lNT /t 50Hz = Integer
? OPTIMUM INTEGRATION CURRENT
I INT = 4 μ A
? FULL-SCALE ANALOG INPUT VOLTAGE
V lNFS (Typ) = 200mV or 2V
? INTEGRATE RESISTOR
V INFS
R INT = -----------------
? INTEGRATE CAPACITOR
( t INT ) ( I INT )
C INT = --------------------------------
? INTEGRATOR OUTPUT VOLTAGE SWING
( t INT ) ( I INT )
V INT = --------------------------------
? DISPLAY COUNT
COUNT = 1000 × ---------------
V REF
? CONVERSION CYCLE
t CYC = t CL0CK x 4000
t CYC = t OSC x 16,000
when f OSC = 48KHz; t CYC = 333ms
? COMMON MODE INPUT VOLTAGE
(V- + 1V) < V lN < (V+ - 0.5V)
? AUTO-ZERO CAPACITOR
0.01 μ F < C AZ < 1 μ F
? REFERENCE CAPACITOR
0.1 μ F < C REF < 1 μ F
? V COM
Biased between V+ and V-
? V COM ? V+ - 2.8V
Regulation lost when V+ to V- < ? 6.8V;
If V COM is externally pulled down to (V + to V -)/2,
the V COM circuit will turn off
? ICL7126 POWER SUPPLY: SINGLE 9V
V+ - V- = 9V
Digital supply is generated internally
V TEST ? V+ - 4.5V
? ICL7126 DISPLAY: LCD
Type: Direct drive with digital logic supply amplitude
? V INT MAXIMUM SWING:
(V- + 0.5V) < V INT < (V+ - 0.5V), V INT (Typ) = 2V
Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE
(COUNTS)
2999 - 1000
SIGNAL INTEGRATE
PHASE FIXED
1000 COUNTS
DE-INTEGRATE PHASE
0 - 1999 COUNTS
TOTAL CONVERSION TIME = 4000 x t CLOCK = 16,000 x t OSC
5
FN3084.5
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