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参数资料
| 型号： | ICPL2533 |
| 厂商： | ISOCOM COMPONENTS LTD |
| 元件分类： | 光电耦合器 |
| 英文描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.25 Mbps |
| 文件页数： | 3/4页 |
| 文件大小： | 66K |
| 代理商： | ICPL2533 |
SWITCHING SPECIFICATIONS AT T
A = 25°C ( VCC = 5V Unless otherwise noted )
0
I
F
V
O
1.3V
5V
t
PHL
t
PLH
V
OL
DB91038-AAS/A3
7/12/00
2
I
F Monitor
100
R
L
V
O
C
L = 15pF
8
7
6
5
I
F
1
4
3
10% Duty Cycle
1/f < 100
s
5V
PARAMETER
SYM DEVICE
MIN TYP MAX UNITS
TEST CONDITION
0.8
1.5
s
I
F = 8mA,RL= 7.5k
Propagation Delay Time
t
PHL
(note 10 )
to Logic Low at Output ( fig 1 )
0.3
1.5
s
I
F = 16mA,RL= 4.7k,
(note11 )
1.0
2.5
s
I
F = 8mA,RL= 7.5k,
Propagation Delay Time
t
PLH
(note 10 )
to Logic High at Output ( fig 1 )
1.1
2.5
s
I
F = 16mA,RL= 4.7k,
(note11 )
1000
V/
s
I
F = 0mA, VCM = 10VPP
Common Mode Transient
R
L= 7.5k,(note9,10 )
Immunity at Logic High
CM
H
Level Output ( fig 2 )
1000
V/
s
I
F = 0mA, VCM = 10VPP
R
L = 4.7k,(note9,11 )
-1000
V/
s
I
F = 8mA,VCM = 10VPP
Common Mode Transient
R
L = 7.5k,(note9,10 )
Immunity at Logic Low
CM
L
Level Output ( fig 2 )
-1000
V/
s
I
F = 16mA,VCM= 10VPP
R
L = 1.9k,(note9,11 )
NOTES:-
1.
Derate linearly above 70oC free air temperature at a rate of 0.8 mA/°C.
2.
Derate linearly above 70oC free air temperature at a rate of 1.6 mA/°C.
3.
Derate linearly above 70oC free air temperature at a rate of 0.9 mW/°C.
4.
Derate linearly above 70oC free air temperature at a rate of 1.0 mW/°C.
5.
Each channel .
6.
CURRENT TRANSFER RATIO is defined as the ratio of output collector current,I
O , to the forward LED
input current, I
F times 100%.
7.
Device considered a two-terminal device: pins 1,2,3,and 4 shorted together and pins 5,6,7,and 8 shorted
together.
8.
Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
9.
Common mode transient immunity in Logic High level is the maximum tolerable (positive) dVcm/dt on
the leading edge of the common mode pulse V
CM to assure that the output will remain in a Logic High
state (i.e. V
O > 2.0V).
Common mode transient immunity in Logic Low level is the maximum tolerable
(negative) dVcm/dt on the trailing edge of the common mode pulse signal, V
CM to assure that the output
will remain in Logic Low state (i.e. V
O< 0.8V).
10. The 7.5k
load represents 1 LSTTL unit load of 0.36mA and a 20k pull-up resistor.
11. The 4.7k
load represents 1 LSTTL unit load of 0.36mA and a 8.2k pull-up resistor.
12. The 2500 V
RMS / 1minute capability is validated by a factory 3.1k VRMS / 1 second dielectric test.
FIG.1 SWITCHING TEST CIRCUIT
PULSE
GENERATOR
Z
O = 50
t
r = 5ns
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