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| 型号： | ICS2510G |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 2510 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.173 INCH, TSSOP-24 |
| 文件页数： | 1/6页 |
| 文件大小： | 149K |
| 代理商： | ICS2510G |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS2510
Advance Information
Block Diagram
3.3V Phase-Lock Loop Clock Driver
2510 Rev - 11/13/98
Pin Configuration
24 Pin TSSOP
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
The ICS2510 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2510 operates at 3.3V VCC
and drive up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter copies
of CLKIN. Output signal duty cycles are adjusted to 50
percent, independent of the duty cycle at CLKIN. Outputs
can be enabled or disabled via control (OE) inputs. When the
OE inputs are high, the outputs align in phase and frequency
with CLKIN; when the OE inputs are low, the outputs are
disabled to the logic low state.
The ICS2510 does not require external RC filter components.
The loop filter for the PLL is include on-chip, minimizing
component count, board space, and cost. The test mode shuts
off the PLL and connects the input directly to the output
buffer. This test mode, the ICS2510 can be use as low skew
fanout clock buffer device. The ICS2510 comes in 24 pin
173mil Thin Shrink Small-Outline package (TSSOP) package.
Meet PC SDRAM Registered DIMM Specification
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of five and one
bank of four outputs
Operating frequency 25MHz to 125Mhz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
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