参数资料
型号: ICS300M-11LFT
元件分类: 时钟产生/分配
英文描述: 135 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: SOIC-8
文件页数: 2/4页
文件大小: 54K
代理商: ICS300M-11LFT
MDS300-11A
2
Revision 11118
Printed 11/10/98
Integrated Circuit Systems 1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
ICRO
CLOCK
ICS300-11
QTClock 125 MHz Clock Synthesizer
Pin Assignment
1
8
2
3
4
7
6
5
X1/ICLK
VDD
GND
DC
X2
PDTS
DC
125M
Number
Name
Type
Description
1
X1/ICLK
I
Crystal connection. Connect to 20 MHz crystal or clock.
2
VDD
P
Connect to +3.3V or +5V.
3
GND
P
Connect to ground.
4
DC
-
Don't Connect anything to this pin.
5
125M
O
125 MHz clock output whose amplitude matches VDD.
6
DC
-
Don't Connect anything to this pin.
7
PDTS
I
Powers down PLL, and puts output into high impedance state, when low.
8
X2
O
Crystal connection to 20 MHz crystal. Leave unconnected for clock input.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
External Components / Crystal Selection
The ICS300 requires a 0.01F decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS300 to minimize lead inductance. No external power supply filtering is required
for this device. A 33
terminating resistor can be used next to the CLK pin. The total on-chip capacitance
is approximately 16 pF, so a parallel resonant, fundamental mode crystal should be used. For crystals with
a specified load capacitance greater than 16 pF, crystal capacitors can be connected from each of the pins
X1 and X2 to Ground. The value (in pF) of these crystal caps should be = (CL-16)*2, where CL is the
crystal load capacitance in pF. These external capacitors are only required for applications where the exact
frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on either).
Device Configuration
The ICS300 QTClock has many programming options, so the two character alphanumeric programming
code (in this case, the -11) must be specified when ordering parts.
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