参数资料
型号: ICS307M-02
元件分类: 时钟产生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO16
封装: 0.150 INCH, SOIC-16
文件页数: 5/9页
文件大小: 196K
代理商: ICS307M-02
SERIALLY PROGRAMMABLE CLOCK SOURCE
MDS 307-01/02 G
5
Revision 031606
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297 -1 201 www.icst.com
ICS307-01/02
Bypass Mode
If R6:0 is programmed to 0000000, the PLL is powered down and bypassed; the reference frequency will
come from both CLK1 and CLK2. It is possible to generate glitches going into and out of this mode.
Configuring the ICS307
The ICS307 can be programmed to set the output functions and frequencies. The three data bytes are
written in DATA pin in this order:
C1 is loaded into the port first and R0 last.
R6:R0
Reference Divder Word (RDW)
V8:V0
VCO Divider Word (VDW)
S2:S0
Output Divider Select (OD)
F1:F0
Function of CLK2 Output
TTL
Duty Cycle Settings
C1:C0
Internal Load Capacitance for Crystal
The ICS307 can be reprogrammed at any time during operation. If R6:0, V8:0, TTL, or C1:0 are changed, the
frequency will transition smoothly to the new value over about 1 ms, without glitches or short cycles. If S2:0 is
changed, it is possible to generate glitches on CLK1 and also on CLK2 for F1:0 = 1 1.
Changing F1:0 will generate glitches on CLK2.
Power up default values for ICS307-02
The input frequency will come from both outputs.
A warning about using the default configuration with input frequencies lower than 13.75 MHz
The VCO will run only as low as its minimum frequency, which is guaranteed to be no more than 55 MHz.
So, in the powerup default condition, the PLL is guaranteed to lock to the input frequency down to 55/4 =
13.75 MHz. However, the part will typically run much slower. The typical minimum VCO frequency is about
30 - 40 MHz, depending on voltage, temperature, and lot variation; so in the powerup default setting, the
CLK2 output will be a minimum of 7.5 - 10 MHz even if the input frequency is lower than that. The output is
not locked to the reference input and so the frequency is not very stable and the phase noise is higher. In
this condition, the CLK2 output will accurately provide the reference frequency down to 0 Hz because this
signal path bypasses the PLL.
Power-down Mode
When the PDTS pin is pulled low, the chip will enter the power-down mode, where the output clocks are
tri-stated and the rest of the chip is powered down. The chip can be programmed during power-down
mode, however, if the chip is programmed during operation and enters power-down mode, the registers will
return to their settings and not reset when exiting power-down mode (PDTS pin is pulled high).
C1
C0
TTL
F1
F0
S2
S1
S0
V8
V7
V6
V5
V4
V3
V2
V1
V0
R6
R5
R4
R3
R2
R1
R0
MSB
LSB
MSB
LSB
MSB
LSB
001000
11
0000
0100
000
00110
相关PDF资料
PDF描述
ICS308RI 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS308R-T 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS308R 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS309R 200 MHz, OTHER CLOCK GENERATOR, PDSO20
ICS309RI 200 MHz, OTHER CLOCK GENERATOR, PDSO20
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