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参数资料
| 型号： | ICS348RPLFT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.150 INCH, ROHS COMPLIANT, SSOP-20 |
| 文件页数： | 3/7页 |
| 文件大小： | 154K |
| 代理商： | ICS348RPLFT |
Quad PLL Field Programmable VersaClock Synthesizer
MDS 348 H
3
Revision 051705
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS348
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS348 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33
series termination
resistor, if needed, should be placed close to the clock
output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers
ICS348 Configuration Capabilities
The architecture of the ICS348 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS348 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user’s target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
OutputFreq
REFFreq
OutputDivide
-------------------------------------- M
N
-----
=
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS348RPT | 功能描述:IC CLK SYNTHESIZER QUAD 20-QSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:VersaClock™ 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS348T | 制造商:ADAM-TECH 制造商全称:Adam Technologies, Inc. 功能描述:IC SOCKETS SINGLE & DUAL ROW SOCKETS |
| ICS3726-02 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726-12 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726M-02 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
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