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参数资料
| 型号： | ICS355R-XX |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.150 INCH, QSOP-20 |
| 文件页数： | 2/5页 |
| 文件大小： | 74K |
| 代理商： | ICS355R-XX |
MDS 355 B
2
Revision 111000
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
ICS355
Triple PLL Quick Turn Clock Synthesizer
PRELIMINARY INFORMATION
Pin Assignments
Number
Name
Type Description
1
X1/ICLK
XI
Crystal connection. Connect to fundamental mode crystal or clock input.
2
S0
I
Select pin 0 for frequency table/chip control. Internal pull-up resistor.
3
S1
I
Select pin 1 for frequency table/chip control. Internal pull-up resistor.
4
CLK9
O
Clock output.
5
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 16 and 19.
6
GND
P
Connect to ground.
7
CLK1
O
Clock output.
8
CLK2
O
Clock output.
9
CLK3
O
Clock output.
10
CLK4
O
Clock output.
11
CLK8
O
Clock output.
12
CLK7
O
Clock output.
13
CLK6
O
Clock output.
14
CLK5
O
Clock output.
15
GND
P
Connect to ground.
16
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 19.
17
S2
I
Select pin 2 for frequency table/chip control. Internal pull-up resistor.
18
PDTS
I
All-chip Power Down when low. Note 1.
19
VDD
P
Connect to +3.3V or +5V. Must be same voltage as pins 5 and 16.
20
X2
XO Crystal connection. Leave unconnected for clock input.
Pin Descriptions
Key: XI, XO = crystal connections, I = Input, O = output, P = power supply connection
Note 1: All outputs are internally high impedance with a weak internal pull-down resistor. When
PDTS is active, it is possible to overdrive the output pins for board-level testing.
1
16
2
3
4
15
14
13
CLK9
CLK3
S0
VDD
20 pin (150 mil) SSOP
5
6
7
8
12
11
10
9
CLK4
VDD
S1
X1/ICLK
X2
S2
CLK7
CLK8
CLK2
CLK1
18
17
19
20
GND
VDD
CLK6
CLK5
GND
PDTS
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