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参数资料
| 型号： | ICS355R-XXT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.150 INCH, QSOP-20 |
| 文件页数： | 3/5页 |
| 文件大小： | 74K |
| 代理商： | ICS355R-XXT |
MDS 355 B
3
Revision 111000
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA95126(408) 295-9800tel www.icst.com
ICS355
Triple PLL Quick Turn Clock Synthesizer
PRELIMINARY INFORMATION
External Components / Crystal Selection
The ICS355 requires a 0.01F decoupling capacitor to be connected between VDD and GND on pins 5
and 6, and another between pins 16 and 15. These must be connected close to the ICS355 to minimize
lead inductance. No external power supply filtering is required for this device. A 33
series terminating
resistor can be used next to each CLK pin. For a crystal input, a parallel resonant, fundamental mode
crystal should be used. Crystal capacitors must be connected from each of the pins X1 and X2 to Ground.
The value (in pF) of these crystal caps should equal (CL-6pf)*2, where CL is the crystal load capacitance in
pF. As an example, for a crystal with 16 pF load capacitance, each crystal capacitor would be XX pF
[(16 - 6pf)*2 = 20].
For a clock input, connect to X1/ICLK and leave X2 unconnected (no capacitors on either X1 or X2).
Frequency Select Table
The ICS355 can be configured so that one PLL provides up to 8 frequency selections. For example, CPU
frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information
should be indicated on the Order Form when the ICS355 is initially defined.
Device Configuration
The ICS355 QTClock provides the facility for up to 9 clock outputs. The outputs are derived from either
the reference input or from one of the 3 PLLs. All chip functions are controlled from an OTP ROM which
has 3 input control lines (S2, S1, S0), giving a total of 8 address locations. Each address location gives
control of the following:
1) Each output can be turned off individually
2) The internal dividers for each PLL are controlled to generate any required frequency.
3) Each PLL can be turned off (powered down) individually.
4) The spread spectrum function available on PLLA can be enabled or disabled
5) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.
6) Up to four low skew copies of the same clock can be enabled.
This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could
be dedicated to enabling/disabling spread spectrum, a second could be used to control the power of the
chip by shutting down PLLs and outputs when not used. The third could be used to change the output
clock frequencies.
The specification is complete when the ICS355 QTClock Order Form accompanies this data sheet. The
order form lists the input and CLK actual frequencies, as well as any other available options. This unique
configuration is given a two character alphanumeric programming code (ICS355-xx), which must be
specified when referring to samples.
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相关代理商/技术参数 |
参数描述 |
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| ICS3726-02 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726-12 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726M-02 | 制造商:ICS 制造商全称:ICS 功能描述:HIGH PERFORMANCE VCXO |
| ICS3726M-02LF | 功能描述:IC VCXO 24-36MHZ 12MA TTL 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS3726M-02LFT | 功能描述:IC VCXO HI PERF 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
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