参数资料
型号: ICS3727XPM
元件分类: 时钟产生/分配
英文描述: 36 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 3/7页
文件大小: 126K
代理商: ICS3727XPM
LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO
MDS 3727XP A
3
Revision 102004
In te gr ated Circuit Systems 525 Ra ce Street, San Jose, CA 9512 6 tel (4 08) 297-1 201 www.icst.com
ICS3727XP
PRELIMINARY INFORMATION
External Component Selection
The ICS3727XP requires a minimum number of
external components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pin 2) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 5) and the load is over 1 inch, series termination
should be used. To series terminate a 50
trace (a
commonly used trace impedance) place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Quartz Crystal
The ICS3727XP VCXO function consists of the
external crystal and the integrated VCXO oscillator
circuit. To assure the best system performance
(frequency pull range) and reliability, a crystal device
with the recommended parameters (shown below)
must be used, and the layout guidelines discussed in
the following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS3727XP incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS3727XP is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25°C
±20 ppm
Temperature Stability
±30 ppm
Aging
±20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS3727XP. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS3727XP to 3.3 V. Connect
pin 3 of the ICS3727XP to the second power supply.
Adjust the voltage on pin 3 to 0V. Measure and record
the frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3 V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
ftarget = nominal crystal frequency
errorxtal =actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than ±25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
Error
10
6
x
f
3.0V
f
tet
arg
()
f
0V
f
tet
arg
()
+
f
tet
arg
------------------------------------------------------------------------------
error
xtal
=
相关PDF资料
PDF描述
ICS3771G-18LF 3771 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS3771G-18T 3771 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS377R-XX 200 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS377R-XXT 200 MHz, OTHER CLOCK GENERATOR, PDSO28
ICS377R-XX 200 MHz, OTHER CLOCK GENERATOR, PDSO28
相关代理商/技术参数
参数描述
ICS3727XPMT 制造商:ICS 制造商全称:ICS 功能描述:LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO
ICS3771G-18LF 功能描述:IC CLK SOURCE DTV/STB 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
ICS3771G-18LFT 功能描述:IC CLK SOURCE DTV/STB 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS,LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP(7x7) 包装:带卷 (TR)
ICS3840BLF 制造商:ICS 制造商全称:ICS 功能描述:DDR SDRAM MUX
ICS3947AYIN 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER