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参数资料
| 型号： | ICS376R-XX-LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 0.150 INCH, QSOP-20 |
| 文件页数： | 4/5页 |
| 文件大小： | 69K |
| 代理商： | ICS376R-XX-LF |
MDS 376 C
4
Revision 051001
Integrated Circuit Systems, Inc. 525 Race Street,San Jose,CA,95126 (408) 295-9800 tel www.icst.com
ICS376
Quad PLL with VCXO Quick Turn Clock Synthesizer
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
Commercial version
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3.13
3.46
V
Input High Voltage, VIH
PDTS, S0, S1, S2
2
V
Input Low Voltage, VIL
PDTS, S0, S1, S2
0.8
V
Output High Voltage, VOH
IOH=-4mA
VDD-0.4
V
Output High Voltage, VOH
IOH=-12mA
2.4
V
Output Low Voltage, VOL
IOL=12mA
0.4
V
IDD Operating Supply Current
TBD
mA
Short Circuit Current
CLK output
±50
mA
On-Chip Pull-up Resistor, inputs
TBD
k
On-Chip Pull-down Resistor, outputs
TBD
Input Capacitance, inputs
4
pF
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, crystal input
13
27
MHz
Output Frequency
2
200
MHz
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle (Note 1)
at VDD/2
45
49 to 51
55
%
Absolute Clock Period Jitter
Deviation from mean
±TBD
ps
One Sigma Clock Period Jitter
TBD
ps
Pin to Pin Skew
Low skew outputs
-250
250
ps
Power-up time
PDTS goes high until CLKout
8
20
ms
Electrical Specifications
Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the ICS376
QTClock Order Form for each programmed version.
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