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参数资料
| 型号： | ICS3771G-18T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 3771 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件页数： | 2/8页 |
| 文件大小： | 175K |
| 代理商： | ICS3771G-18T |
ICS3771-18
DTV, STB CLOCK SOURCE
SYNTHESIZERS
IDT / ICS DTV, STB CLOCK SOURCE
2
ICS3771-18
REV B 111307
Pin Assignment
16-pin TSSOP
Output Clock Selection Table (MHz)
*OFF = output is driven HIGH.
Pin Descriptions
12
1
11
2
10
CLKIN
NC
3
9
VDD
4
AVDD
OE
5
NC
6
FS1
7
GNDA
8
GND
CLK1
VDDL
REFOUT2
FS0
REFOUT1
CLK2
16
15
14
13
OE FS1 FS0
CLK1/CLK2
REFOUT1/REFOUT2
000
OFF*
27
001
OFF*
27
010
OFF*
27
011
OFF*
27
1
0
27
1
0
1
27.027
27
1
0
74.250
27
1
74.17582418
27
Pin
Numbe
r
Pin
Name
Pin
Type
Pin Description
1
CLKIN
Input
Reference clock input. Connect to a 27 MHz external clock.
2
VDD
Power
Power supply.
3
AVDD
Power
Power supply. Connect to 3.3 V.
4
NC
–
No connect. Leave floating.
5
GNDA
Power
Analog ground.
6
GND
Power
Connect to ground.
7
REFOUT
Output
Reference Clock output 2. See table above.
8
REFOUT
Output
Reference Clock output 1. See table above.
9
CLK2
Output
Selectable Clock output 2. See table above.
10
FS0
Input
Frequency select pin 0. Weak internal pull-up. See table above.
11
VDDL
Power
Power supply. Connect to 3.3 V.
12
CLK1
Output
Selectable Clock output 1. See table above
13
GND
Power
Connect to ground.
14
FS1
Input
Frequency select pin 1. Weak internal pull-up. See table above.
15
OE
Output
Output Enable pin. Weak internal pull-up. See table above.
16
NC
–
No connect. Leave floating.
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