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参数资料
| 型号： | ICS377R-XX |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, QSOP-28 |
| 文件页数： | 3/5页 |
| 文件大小： | 73K |
| 代理商： | ICS377R-XX |
MDS 377 B
3
Revision 050401
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA, 95126 (408) 295-9800 www.icst.com
ICS377
Quad PLL with VCXO
Quick Turn Clock Synthesizer
PRELIMINARY INFORMATION
External Components / Crystal Selection
The ICS377 requires five 0.01F decoupling capacitors to be connected between VDD and GND pairs. It is
recommended that these be placed between VDD and GND pairs on pin 5 and 8, pin 6 and 10, pin 22 and 19, pin
23 and 21, and pin 24 and 20. These must be connected close to the ICS377 to minimize lead inductance. No
external power supply filtering is required for this device. A 33
series terminating resistor can be used next to
each CLK pin. The input crystal must be connected as close to the chip as possible. The input crystal should be a
parallel mode, pullable, AT cut, with 14 pF load capacitance. See previous page for crystal specifications. Consult
ICS for recommended suppliers. IMPORTANT - read application note MAN05 before laying out the PCB.
Frequency Select Table
The ICS377 can be configured so that one PLL provides up to 8 frequency selections. For example, CPU
frequencies of 66.7 MHz, 100.0 MHz, 133.3 MHz, and 166.7 MHz could be included. This information should be
indicated on the Order Form when the ICS377 is initially defined.
Device Configuration
The ICS377 QTClock provides the facility for up to 8 clock outputs. The outputs are derived from either the reference
input or from one of the 4 PLLs. All chip functions are controlled from an OTP ROM which has 3 input control lines
(S2, S1, S0), giving a total of 8 address locations. Each address location gives control of the following:
1) Each output can be turned off individually.
2) The internal dividers for each PLL are controlled to generate any required frequency.
3) Each PLL can be turned off (powered down) individually.
4) The output divide and control logic can be configured to bring the appropriate clock to the correct pin.
5) Up to four low skew copies of the same clock can be enabled.
This chip architecture provides the user with unrivaled flexibility. For example, one of the input pins could be used to
control the power of the chip by shutting down PLLs and outputs when not used. A second could be used to
change the output clock frequencies.
The specification is complete when the ICS377 QTClock Order Form accompanies this data sheet. The order form
lists the input and CLK actual frequencies, as well as any other available options. This unique configuration is given a
two character alphanumeric programming code (ICS377-xx), which must be specified when referring to samples.
Crystal Specifications
Correlation (load) capacitance
14 pF
Initial accuracy
±20 ppm maximum
Drift over temperature and aging
±50 ppm maximum
C0/C1 ratio
250 maximum
ESR
35
maximum
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