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参数资料
| 型号： | ICS409MT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 2/6页 |
| 文件大小： | 151K |
| 代理商： | ICS409MT |
ICS409
PC PERIPHERAL CLOCK
CLOCK SYNTHESIZER
IDT / ICS PC PERIPHERAL CLOCK
2
ICS409
REV C 111005
Pin Assignment
40/80M Frequency Selection
Note: See below for operations of frequency selection
Pin Descriptions
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS409 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X1 to ground.
The value (in pF) of these crystal caps should equal (CL
-6pF)*2. In this equation, CL= crystal load capacitance
in pF. Example: For a crystal with a 15 pF load
1
2
3
OE / L A T
4
GN D
40/ 80M
25M
25 M
X2
VD D
8
7
6
5
X1
8 P i n (150 m il) S O IC
40/80M (pin 5)
Output Freq
0
40M
1
80M
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
OE/LAT
Input
Disables or latches 40/80 MHz output dependant on pin 5 level.
2
X1
Input
Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
3
X2
Input
Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
4
VDD
Power
Connect to voltage supply.
5
40/80M
Input/
Output
40M or 80M selection pin and clock output (see below for operation).
Tri-state when OE/LAT is low.
6
GND
Power
Connect to ground.
7
25M
Output
25 MHz clock output.
8
25M
Output
25 MHz clock output.
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