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参数资料
| 型号： | ICS410MLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 2/5页 |
| 文件大小： | 60K |
| 代理商： | ICS410MLFT |
PC PERIPHERAL CLOCK
MDS 410 A
2
Revision 021202
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ICS410
Pin Assignment
40/80M Frequency Selection
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitors of
0.01
F should be connected between VDD and GND as close to the device as possible. A 33 series
terminating resistor may be used on each output.
Operation of OE/LAT
The 40/80M output clock is selected by a soft pull-up or pull-down on pin 3. On power up the rising edge on
OE latches in the high or low level on pin 3 which starts the appropriate frequency. An external pull-down
or pull-up resistor (10k
) on pin 3 will select an output frequency of 40 or 80 MHz respectively. Any
low-to-high transistion on OE/LAT after power up will latch the logic level on pin 3. The 24.576 MHz and
40/80 MHz are disabled and tri-stated when OE is low.
1
2
3
X1
4
VD D
GN D
OE / L A T
24 . 5 7 6 M
40 / 8 0 M
50 M
8
7
6
5
X2
8 P i n (1 5 0 m i l) S O IC
Pin 3 (40/80)
Freq
040M
180M
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1
Input
Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
2
24.576M
Output
24.576 MHz clock output. Tri-state when OE/LAT is low.
3
40/80M
Output
40M or 80M selectable clock output. Latched on rising edge of
OE.Tri-state 40/80 MHz when OE/LAT is low.
4
50M
Output
50 MHz clock output.
5
GND
Power
Connect to ground.
6
VDD
Power
Connect to voltage supply.
7
OE/LAT
Input
Output selects/disables 40/80M output.
8
X2
Input
Crystal connection. Connect to 14.31818 MHz parallel mode crystal.
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