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参数资料
| 型号： | ICS4231M-03LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 33 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 0.150 INCH, LEAD FREE, SOIC-8 |
| 文件页数： | 3/7页 |
| 文件大小： | 231K |
| 代理商： | ICS4231M-03LFT |
LOW EMI CLOCK GENERATOR
ICS4231-03
MDS 4231-03 A
3
Revision 110404
In te gr ated Circuit Systems
● 5 25 Race Stree t, San Jose, CA 951 26 ● tel (408) 297-1 201 ● www.icst.com
External Components
The ICS4231-03 requires a minimum number of
external components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
trace (a commonly used
trace impedance) place a 33
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
value of these capacitors is given by the following
equation:
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI the 33
series termination resistor,
if needed, should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS4231-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS4231-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
°C
Storage Temperature
-65 to +150
°C
Junction Temperature
125
°C
Soldering Temperature
260
°C
ICS4231-03
Low EMI Clock Generator
TSD
IDT / ICS Low EMI Clock Generator
ICS4231-03
3
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相关代理商/技术参数 |
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| ICS4231M-03T | 功能描述:IC CLOCK GENERATOR LOW EMI 8SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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| ICS426G | 制造商:ICS 制造商全称:ICS 功能描述:Serial ATA/Fibre Channel Clock Synthesizer |
| ICS426GT | 制造商:ICS 制造商全称:ICS 功能描述:Serial ATA/Fibre Channel Clock Synthesizer |
| ICS43001AI22L | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL/LVCMOS-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
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