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参数资料
| 型号： | ICS525-01RILT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, LEAD FREE, MO-153, SSOP-28 |
| 文件页数： | 4/9页 |
| 文件大小： | 168K |
| 代理商： | ICS525-01RILT |
OSCaRTM User Configurable Clock
MDS 525-01/02 M
4
Revision 062304
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-01/02 requries two 0.01F decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance. No external power supply filtering is
required for this device.
External Resistors
A 33
series terminating resistor can be used next to
the CLK and REF pins.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the table on page 2.
To replace a standard oscillator, users should connect
the divider select input pins directly to ground (or VDD,
although this is not required because of internal
pull-ups) during Printed Circuit Board layout. The
ICS525-01/02 will automatically produce the correct
clock when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
ICS525-01 Settings
The output of the ICS525-01 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 1 to 127 (0 not
permitted)
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 not
permitted)
Output Divider (OD) = values on page 3
Also, the following operating ranges should be
observed:
See table on page 3 for full details of maximum
output.
ICS525-02 Settings
The output of the ICS525-02 can be determined by the
following simple equation:
Where:
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 3
Also, the following operating ranges should be
observed:
See table on page 3 for full details of maximum
output.
CLK Frequency
Input Frequency 2x
VDW 8
+
()
RDW 2
+
() OD
---------------------------------------------
×
=
10M Input Frequencyx2x
VDW 8
+
()
RDW 2
+
()
-------------------------------200M 3.3V
()or320M 5v )
(
)
<<
200kHz InputFrequency
RDW 2
+
()
-----------------------------------------------
<
CLK Frequency
Input Frequency 2x
VDW 8
+
()
RDW 2
+
() OD
---------------------------------------------
×
=
10M Input Frequencyx2x
VDW 8
+
()
RDW 2
+
()
------------------------------- 240M 3.3V
()or400M 5v )
(
)
<<
200kHz InputFrequency
RDW 2
+
()
-----------------------------------------------
<
相关PDF资料 |
PDF描述 |
|---|---|
| ICS525-01RT | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525-02RILF | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525-02RT | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525-02RILF | 140 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| ICS525R-02ILF | 250 MHz, OTHER CLOCK GENERATOR, PDSO28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS525-01RIT | 功能描述:IC CLOCK USER CONFIGURE 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:OSCaR™ 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS525-01RLF | 功能描述:IC CLK USER CONFIGURABLE 28-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:OSCaR™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS525-01RLFT | 功能描述:IC CLK USER CONFIGURABLE 28-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:OSCaR™ 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS525-01RT | 功能描述:IC CLOCK USER CONFIGURE 28-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:OSCaR™ 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS525-02 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Clock |
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