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参数资料
| 型号： | ICS525-01RT |
| 厂商： | MICREL INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 160 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封装： | 0.150 INCH, SSOP-28 |
| 文件页数： | 3/5页 |
| 文件大小： | 79K |
| 代理商： | ICS525-01RT |
ICS525
OSCaR User Configurable Clock
MDS525E
3
Revision 3098
Printed 5/7/98
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
CLK frequency = Input frequency 2
(VDW+8)
(RDW+2)(OD)
Determining (setting) the output frequency
The user has full control in setting the desired output frequency over the range shown in the table on
page 2. To replace a standard oscillator, a user should connect the divider select input pins directly to
ground (or VDD, although this is not required because of internal pull-ups) during Printed Circuit Board
layout, so that the ICS525 automatically produces the correct clock when all components are soldered. It is
also possible to connect the inputs to parallel I/O ports to switch frequencies. Contact MicroClock/ICS for
tips when using this mode.
The output of the ICS525 can be determined by the following simple equation:
The dividers are expressed as integers, so that if a 66.66 MHz output is desired from a 14.31818 input, the
Reference Divider Word (RDW) should be 59, and the VCO Divider Word (VDW) should be 276, with
an Output divider (OD) of 2. In this example, R6:R0 is 0111011, V8:V0 is 100010100, and S2:S0 is 001.
Since all of these inputs have pull-up resistors, it is only necessary to ground the zero pins, namely V7, V6,
V5, V3, V1, V0, R6, R2, S2, and S1.
To determine the best combination of VCO, reference, and output divider, use the ICS525 Calculator on
our Web site: http://www.microclock.com. This online form is easy to use and quickly shows you up to
three options for these settings.
You may also fax this page to MicroClock/ICS at 408 295 9818(fax), or send an e-mail to
sales@microclock.com. Be sure to indicate the following:
Your Name ________________ Company Name___________________ Telephone_________________
Respond by e-mail (list your e-mail address) __________________or fax number ___________________
Desired input crystal/clock (in MHz) _______________ Desired output frequency________________
VDD = 3.3V or 5V ___________
Duty Cycle: 40-60% _______ or 45-55% required________
Also, the following operating ranges should be observed:
10 MHz < Input frequency 2
(VDW+8)
(RDW+2)
< 320 MHz at 5.0V or
< 200 MHz at 3.3V
200 kHz <
Input Frequency
(RDW+2)
Where
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
VCO Divider Word (VDW) = 4 to 511 (0, 1, 2, 3 are not permitted)
Output Divider (OD) = values on page 2
See Table on Page 2
for full details of
maximum output.
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相关代理商/技术参数 |
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| ICS525-02 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Clock |
| ICS525-03 | 制造商:ICS 制造商全称:ICS 功能描述:PECL Input OSCaR-TM USER Configurable Clock |
| ICS525-04 | 制造商:ICS 制造商全称:ICS 功能描述:OSCaR-TM User Configurable PECL Clock |
| ICS5250708 | 制造商:ICS 制造商全称:ICS 功能描述:LVCMOS User Configurable Clock |
| ICS525-11 | 制造商:ICS 制造商全称:ICS 功能描述:User Configurable Clock |
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