
ICS525-01/02
OSCaR User Configurable Clock
MDS525G
3
Revision10209
Printed 11/12/99
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126(408) 295-9800tel www.icst.com
S2
S1
S0
CLK
Max. Output Frequency (MHz)
pin 5
pin 4
pin 3
Output Divider
VDD = 5V
VDD = 3.3V
0-70
-40 to +85
0-70
-40 to +85
0
10
26
23
18
16
0
1
2
160
140
100
90
0
1
0
8
40
36
25
22
0
1
4
80
72
50
45
1
0
5
50
45
34
30
1
0
1
7
40
36
26
23
1
0
9
33.3
30
20
18
1
6
53
47
27
24
ICS525-01 Output Divider and Maximum Output Frequency Table
S2
S1
S0
CLK
Max. Output Frequency (MHz)
pin 5
pin 4
pin 3
Output Divider
VDD = 5V
VDD = 3.3V
0-70
-40 to 85
0-70
-40 to85
0
6
0
1
2
0
1
0
8
0
1
4
1
0
5
1
0
1
7
1
0
1
3
ICS525-02 Output Divider and Maximum Output Frequency Table
All Above TBD
External Components / Crystal Selection
The ICS525 requires two 0.01F decoupling capacitors to be connected between VDD and GND, one on
each side of the chip. They must be connected close to the ICS525 to minimize lead inductance. No
external power supply filtering is required for this device. A 33
terminating resistor can be used next to
the CLK and REF pins. The approximate total on-chip capacitance for a crystal is shown in the table
below, so a parallel resonant, fundamental mode crystal with this value of load (correlation) capacitance
should be used. For example, using the ICS525-01 with crystals having a specified load capacitance greater
than 16 pF, crystal capacitors may be connected from each of the pins X1 and X2 to Ground as shown in
the Block Diagram on page 1. The value (in pF) of these crystal caps should be = (CL-16)*2, where CL is
the crystal load capacitance in pF. These external capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to X1 and leave X2 unconnected (no capacitors on
either).
Device
Capacitance
ICS525-01
16pF
ICS525-02
TBD
Approximate On-Chip Capacitance