参数资料
型号: ICS548G-05LFT
元件分类: 时钟产生/分配
英文描述: 49.152 MHz, OTHER CLOCK GENERATOR, PDSO16
封装: ROHS COMPLIANT, MO-153, TSSOP-16
文件页数: 1/6页
文件大小: 135K
代理商: ICS548G-05LFT
ICS548-05C
MDS 548-05C C
1
Revision 020606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com
T1/E1 Clock Multiplier
Description
The ICS548-05C is a low-cost, low-jitter,
high-performace clock synthesizer designed to
produce x16 and x24 clocks from T1 and E1
frequencies. Using ICS’ patented analog/digital Phase-
Locked Loop (PLL) techniques, the device uses a
crystal or clock input to synthesize popular
communications frequencies. Power down modes allow
the chip to turn off completely, or the PLL and clock
output to be turned off separately.
ICS manuafactures the largest variety of
communications clock synthesizers for all applications.
Consult ICS to eliminate VCXO’s, crystals, and
oscillators from your board.
Features
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Ideal for telecom/datacom chips
Replaces oscillators
3.3 V or 5 V operation
Uses a crystal or clock input
Produces 24.704, 37.056, 32.768, or 49.152 MHz
Includes Power-down features
Advanced, low-power, sub-micron CMOS process
See also the MK2049-34 for generating
Industrial temperature range available
Block Diagram
X1/ICLK
X2
Input
Buffer/
Crystal
Oscillator
1.544 MHz or
2.048 MHz
clock or crystal
input
Optional crystal
capacitors
CLK
REFOUT
MSEL
X16 or x24
PLL/Clock
Synthesis
Circuitry
REFEN
PDCLK
相关PDF资料
PDF描述
ICS552G-02ILF 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS552G-02IT 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS552G-03ILFT 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS552G-03I 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS552G-03T 552 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
相关代理商/技术参数
参数描述
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