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参数资料
| 型号： | ICS548G-06LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 1/5页 |
| 文件大小： | 93K |
| 代理商： | ICS548G-06LF |
ICS548-06
MDS 548-06 B
1
Revision 080103
I n tegra t ed Ci r c uit Systems ● 525 R a ce S t r eet, San Jose, CA 9512 6 ● tel (40 8 ) 295-9 800 ●
w w w. icst . c o m
LOCO PLL CLOCK MULTIPLIER
EOL - DEVICE NOT RECOMMENDED FOR NEW DESIGNS
Description
The ICS548-06 LOCO is a cost effective way to
generate high quality, high frequency clock outputs and
a reference clock from a lower frequency crystal or
clock input. The name LOCO stands for LOw Cost
Oscillator, as it is designed to replace crystal oscillators
in most electronic systems. Using Phase-Locked-Loop
(PLL) techniques, the device uses a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 200MHz.
Stored in the chip’s ROM is the ability to generate nine
different popular multiplication factors, allowing one
chip to output many common frequencies.
Features
Zero ppm multiplication error
Packaged in 16 pin TSSOP
Low power CMOS technology
Easy to cascade with other 5xx series
Input crystal frequency of 5-27 MHz
Input clock frequency of 2-50 MHz
Output clock frequencies up to 200 MHz
Duty Cycle of 45/55 up to 200 MHz
Operating voltage of 3.3 or 5V
Advanced, low power CMOS process
Device not recommended for new designs.
Please contact ICS for replacement information.
Block Diagram
CLK1
Clock
Buffer/
Crystal
Oscillator
X1/ICLK
X2
S1, S0
Crystal or
clock input
PLL
Clock
Synthesis
and
Control
Circuitry
REF
VDD
GND
2
Optional crystal capacitors
2
CLK2
/2
REFSEL
PDCLK2
OE
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| ICS548G-06LF | 200 MHz, OTHER CLOCK GENERATOR, PDSO16 |
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