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参数资料
| 型号： | ICS553MT |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.150 INCH, SOIC-8 |
| 文件页数： | 5/6页 |
| 文件大小： | 89K |
| 代理商： | ICS553MT |
LOW SKEW 1 TO 4 CLOCK BUFFER
MDS 553 B
5
Revision 052501
Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q
w w w. icst . c om
ICS553
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
VDD = 3.3V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
VDD = 5V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
Notes: 1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
tOR
0.8 to 2.0V, CL=15pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15pF
1.5
ns
Propagation Delay
Note 1
3
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
tOR
0.8 to 2.0V, CL=15pF
1.0
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15pF
1.0
ns
Propagation Delay
Note 1
2.6
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
200
MHz
Output Rise Time
tOR
0.8 to 2.0V, CL=15pF
0.7
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15pF
0.7
ns
Propagation Delay
Note 1
2.5
ns
Output to output skew
Note 2
Rising edges at VDD/2
0
50
ps
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS554-01 | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554-01A | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554-01DPK | 制造商:ICS 制造商全称:ICS 功能描述:Clock Divider |
| ICS554-01DWF | 制造商:ICS 制造商全称:ICS 功能描述:Clock Divider |
| ICS554G-01 | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
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