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参数资料
| 型号： | ICS554G-01AILFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:4 200MHZ 16TSSOP |
| 产品培训模块： | Clock Distibution and Generation 1.0 |
| 产品变化通告： | 554G-01AILF(T) Discontinuation 1/Dec/2011 |
| 标准包装： | 2,500 |
| 系列： | ClockBlocks™ |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:4 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | PECL |
| 输出： | LVPECL |
| 频率 - 最大： | 200MHz |
| 电源电压： | 3.15 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 554G-01AILFT |
ICS554-01A
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
PECL BUFFER
IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
3
ICS554-01A
REV D 051310
External Components
The ICS554-01A requires a decoupling capacitor of 0.01
F to be connected between VDD on pin 2 and GND on
pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should be placed as
close to the device as possible.
To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout.
Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output
skew will be degraded. For example, using a 30
series termination on one output (with 33 on the others) will
cause at least 15ps of skew.
Termination for PECL or LVPECL Outputs
The clock layout topology shown below is a typical termination for PECL or LVPECL outputs. The two different
layouts mentioned are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate PECL/LVPECL compatible outputs.
Therefore, termination resistors (DC current path to ground) or current sources must be used for functionality.
These outputs are designed to drive 50 ohm transmission lines. Matched impedance techniques should be used to
maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. The
figures below show two different layouts which are recommended only as guidelines. Other suitable clock layouts
may exist, but it is recommended that board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
PECL or LVPECL Output Termination
LVPECL Output Termination
Z
0 = 50 ohms
F
OUT
F
IN
Z
0 = 50 ohms
50 ohms
C1
RTT
RTT =
Z
0
(V
OH + VOL / VCC -2) -2
1
C1 = 0.1F to 0.01F
Z
0 = 50 ohms
F
OUT
F
IN
Z
0 = 50 ohms
Z
0
3.3 V
5
2
3 2
5
2
Z
0
Z
0
3 2 Z
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS554G-01AIT | 功能描述:IC CLK BUFFER 1:4 200MHZ 16TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:ClockBlocks™ 标准包装:1 系列:HiPerClockS™ 类型:扇出缓冲器（分配），多路复用器 电路数:1 比率 - 输入:输出:2:18 差分 - 输入:输出:是/无 输入:CML，LVCMOS，LVPECL，LVTTL，SSTL 输出:LVCMOS，LVTTL 频率 - 最大:250MHz 电源电压:2.375 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:- 其它名称:800-1923-6 |
| ICS554G-01T | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554GI-01A | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554GI-01AT | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS556-01 | 制造商:ICS 制造商全称:ICS 功能描述:BROADCOM 25 MHZ LVDS CLOCK |
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