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| 型号： | ICS554G-01IT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封装： | 0.173 INCH, TSSOP-16 |
| 文件页数： | 1/5页 |
| 文件大小： | 85K |
| 代理商： | ICS554G-01IT |
ICS554-01
MDS 554-01 C
1
Revision 080103
I n tegra t ed Ci r c uit Systems ● 525 R a ce S t r eet, San Jose, CA 9512 6 ● tel (40 8 ) 295-9 800 ●
w w w. icst . c o m
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
EOL - DEVICE NOT RECOMMENDED FOR NEW DESIGNS
Description
The ICS554-01 is a low skew clock buffer with a single
complimentary PECL input to four PECL outputs. Part
of ICS’ Clock BlocksTM family, this is our lowest skew
PECL clock buffer. For parts which do not require
PECL inputs or outputs, see the ICS553 for a 1 to 4 low
skew buffer, or the ICS552-02 for a 1 to 8 low skew
buffer. For more than 8 outputs see the MK74CBxxx
BuffaloTM series of clock drivers.
ICS makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
Features
Input frequency up to 200MHz
Advanced CMOS process
Outputs are skew matched to within 50ps
Packaged in 16 pin TSSOP
One PECL input to 4 PECL output clock drivers
Operating Voltages of 3.3V to 5V
Industrial temperature
Device not recommended for new designs. Please
contact ICS for replacement information.
Block Diagram
IN
RES
VDD
0.01
mF
1.1k
Q0
VDD
62
270
Q1
VDD
62
270
Q2
VDD
62
270
Q3
VDD
62
270
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| ICS557G-07T | 557 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS554G-01T | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554GI-01A | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS554GI-01AT | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT |
| ICS556-01 | 制造商:ICS 制造商全称:ICS 功能描述:BROADCOM 25 MHZ LVDS CLOCK |
| ICS556-03 | 制造商:ICS 制造商全称:ICS 功能描述:QUAD LVDS OSCILLATOR/BUFFER |
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