参数资料
型号: ICS557GI-05ALF
厂商: IDT, Integrated Device Technology Inc
文件页数: 7/12页
文件大小: 0K
描述: IC CLK SOURCE QUAD PCI 20-TSSOP
产品培训模块: PCI-Express
特色产品: PCI-Express Clock Source
标准包装: 74
系列: PCI Express® (PCIe)
类型: 扩展频谱时钟发生器,扇出缓冲器(分配)
PLL:
主要目的: PCI Express(PCIe)
输入: 时钟,晶体
输出: HCSL,LVDS
电路数: 1
比率 - 输入:输出: 1:4
差分 - 输入:输出: 无/是
频率 - 最大: 200MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 管件
产品目录页面: 1252 (CN2011-ZH PDF)
其它名称: 557GI-05ALF
800-1067
800-1067-5
800-1067-ND
ICS557-05A
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
PCIE SSCG
IDT
QUAD DIFFERENTIAL PCI-EXPRESS GEN1 CLOCK SOURCE
4
ICS557-05A
REV O 112111
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-05A.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01
μF should
be connected between VDD and GND pairs (1,9 and 15,16)
as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (CL-12)*2 in this equation, CL=crystal
load capacitance in pf. For example, for a crystal with a 16
pF load cap, each external crystal cap would be 8 pF.
[(16-12)x2]=8.
Current Reference Source Rr (Iref)
If board target trace impedance (Z) is 50
Ω, then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (IOH) is
equal to 6*IREF.
Load Resistors RL
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown in
detail in the PCI-Express Layout Guidelines section.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
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