- 您现在的位置：买卖IC网 > PDF目录9013 > ICS581G-02ILFT (IDT, Integrated Device Technology Inc)IC CLK MUX GLITCH FREE 16-TSSOP PDF资料下载
参数资料
| 型号： | ICS581G-02ILFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 4/10页 |
| 文件大小： | 0K |
| 描述： | IC CLK MUX GLITCH FREE 16-TSSOP |
| 产品培训模块： | Clock Distibution and Generation 1.0 |
| 标准包装： | 2,500 |
| 系列： | ClockBlocks™ |
| 类型： | 扇出缓冲器（分配），零延迟缓冲 |
| PLL： | 是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 581G-02ILFT |
ICS581-01/02
ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
ZDB AND MULTIPLEXER
IDT / ICS ZERO DELAY GLITCH-FREE CLOCK MULTIPLEXER
3
ICS581-01/02
REV L 051310
Pin Descriptions
Device Operation
The ICS581-01 and ICS581-02 are very similar. Following is
a description of the operation of the ICS581-01 and the
differences of the ICS581-02.
The ICS581-01 is a PLL-based, zero delay, clock
multiplexer. The device consists of an input multiplexer
controlled by SELA that selects between two clock inputs.
The output of the mux drives the reference input of a phase
locked loop. The other input to the PLL comes from a
feedback input pin called FBIN. The output of the PLL drives
four low skew outputs. These chip outputs are therefore
buffered versions of the selected input clock with zero delay
and 50/50 duty cycle.
For correct operation, one of the clock outputs must be
connected to FBIN. In this datasheet, CLK4 is shown as the
feedback, but any one of the four clock outputs can be used.
If output termination resistors are used, the feedback should
be connected before the resistor. It is a property of the PLL
used on this chip that it will align rising edges on FBIN and
either INA or INB (depending on SELA). Since FBIN is
connected to a clock output, this means that the outputs
appear to align with the input with zero delay.
When the input select (SELA) is changed, the output clock
will change frequency and/or phase until it lines up with the
new input clock. This occurs in a smooth, gradual manner
without any short pulses or glitches and will typically take a
few tens of microseconds.
The part must be configured to operate in the correct
frequency range. The table on page two gives the
recommended range.
The four low skew outputs are controlled by two output
enable pins that allow either one, three, or four simultaneous
outputs. If both OE pins are low, the PLL is powered down.
Note that the clock driving the FBIN pin must not be
tri-stated unless the PLL is powered down. Otherwise the
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
S0
Input
Select 0 for frequency range. See table. Internal pull-up.
2
S1
Input
Select 1 for frequency range. See table. Internal pull-up.
3
VDD
Power
Power Supply. Connect to +3.3 V or +5 V.
4
INA
Input
Input Clock A.
5
INB
Input
Input Clock B.
6
GND
Power
Connect to ground.
7
FBIN
Input
Feedback input. Connect to a clock output.
8
OE0
Input
Output enable 0. See table. Internal pull-up.
9
OE1
Input
Output enable 1. See table. Internal pull-up.
10
GND
Power
Connect to ground.
11
CLK4
Output
Low skew clock output.
12
CLK3
Output
Low skew clock output.
13
CLK2
Output
Low skew clock output.
14
CLK1
Output
Low skew clock output.
15
VDD
Power
Power Supply. Connect to +3.3 V or +5 V.
16 (-01)
SELA
Input
Mux select. Selects INA when high. Internal pull-up.
16 (-02)
DIV
Input
Timeout select. See table. Internal pull-up.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B3N-MV-F2 | CONVERTER MOD DC/DC 18.5V 150W |
| VI-J7Y-MZ-F1 | CONVERTER MOD DC/DC 3.3V 16.5W |
| VE-20X-MY-F4 | CONVERTER MOD DC/DC 5.2V 50W |
| ICS270PGILFT | VCXO CLK TRPL PLL PROGR 20-TSSOP |
| VI-B3M-MV-F4 | CONVERTER MOD DC/DC 10V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS581G-02IT | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:ClockBlocks™ 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS581G-02LF | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:ClockBlocks™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS581G-02LFT | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:ClockBlocks™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS581G-02T | 功能描述:IC CLK MUX GLITCH FREE 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:ClockBlocks™ 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS5OSK481 | 制造商:ICS 制造商全称:ICS 功能描述:48 MHz Tiny USB Clock Source |
发布紧急采购，3分钟左右您将得到回复。