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| 型号： | ICS613MLFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULT LOW PHASE 16-SOIC |
| 标准包装： | 2,500 |
| 类型： | 时钟/频率合成器 |
| PLL： | 是 |
| 输入： | 时钟，晶体 |
| 输出： | CMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 157.5MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | 613MLFT |
ICS613
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
IDT / ICS LOW PHASE NOISE CLOCK MULTIPLIER
3
ICS613
REV F 051310
External Component Selection
The ICS613 requires a minimum number of external
components for proper operation.
Decoupling Capacitors
Decoupling capacitors of 0.01
F should be connected
between VDD and GND pairs on pins 4 and 5, pins 6 and 8,
pins 11 and 9, and pins 13 and 14 as close to the ICS613 as
possible. For optimum device performance, the decoupling
capacitors should be mounted on the component side of the
PCB. Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50
trace (a commonly used trace
impedance) place a 33
resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20
.
Crystal Tuning Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground. The value (in pF) of these crystal caps should
equal (CL -6pF)*2. In this equation, CL= crystal load
capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2 = 20].
Reducing Jitter and Phase Noise
For applications that only require one output, jitter and
phase noise can be reduced by tying the unused VDDO to
ground. This will stop the output clock low which will result
in less switching noise on the active output.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS613. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
° C
Storage Temperature
-65 to +150
° C
Soldering Temperature
260
° C
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS613MT | 功能描述:IC CLOCK MULT LOW PHASE 16-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS614-01 | 制造商:ICS 制造商全称:ICS 功能描述:16 pin Intel Graphics Clock Source |
| ICS614M-01 | 制造商:ICS 制造商全称:ICS 功能描述:16 pin Intel Graphics Clock Source |
| ICS614M-01T | 制造商:ICS 制造商全称:ICS 功能描述:16 pin Intel Graphics Clock Source |
| ICS615 | 制造商:ICS 制造商全称:ICS 功能描述:Set-Top Box Clock Source |
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