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参数资料
| 型号： | ICS621NILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 621 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), DSO8 |
| 封装： | 2 X 2 MM, 0.50 MM PITCH, GREEN, DFN-8 |
| 文件页数： | 3/10页 |
| 文件大小： | 230K |
| 代理商： | ICS621NILF |
ICS621
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS621
REV A 062006
Pin Assignment (8-pin SOIC)
Pin Assignment (8-pin DFN)
Pin Descriptions
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01
F
should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33
series
terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS621 is capable of, careful attention must be paid to board layout.
Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they
do not, the output skew will be degraded. For example, using a 30
series termination on one output (with 33 on
the others) will cause at least 15 ps of skew.
1
2
3
4
5
6
7
8
ICLK
Q1
Q2
Q3
Q4
OE
VDD
GND
1
Q3
Q2
GND
VDD
Q1
Q4
ICLK
OE
5
8
4
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK
Input
Clock Input. 3.3 V tolerant input.
2
Q1
Output
Clock Output 1.
3
Q2
Output
Clock Output 2.
4
Q3
Output
Clock Output 3.
5
Q4
Output
Clock Output 4.
6
GND
Power
Connect to ground.
7
VDD
Power
Connect to +1.2 V or +1.8 V.
8
OE
Input
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
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| ICS-624-AGG | 制造商:Samtec Inc 功能描述:CONN DIP SCKT SKT 24 POS 2.54MM SLDR ST TH - Bulk |
| ICS-624-AGT | 制造商:Samtec Inc 功能描述:CONN DIP SCKT SKT 24 POS 2.54MM SLDR ST TH - Bulk |
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