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参数资料
| 型号： | ICS650R-01 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 80 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20 |
| 封装： | 0.150 INCH, SSOP-20 |
| 文件页数： | 3/8页 |
| 文件大小： | 237K |
| 代理商： | ICS650R-01 |
System Peripheral Clock Source
MDS 650-01 F
3
Revision 082505
Integrated Circuit Systems, Inc.
● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS650-01
External Components
The ICS650-01 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
Decoupling capacitors of 0.01F must be connected
between each VDD and GND (pins 4 and 6, pins 16
and 14), as close to the device as possible. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be
used. To series terminate a 50
trace (a commonly
used trace impedance) place a 33
resistor in series
with the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant, 300 ppm or
better (to meet Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to
ground to optimize the initial accuracy. The value of
these capacitors is given by the following equation:
Crystal caps (pF) = (CL - 12) x 2
In the equation, CL is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 8 pF
capacitors should be used. If a clock input is used,
drive it into X1 and leave X2 unconnected.
13
14.318M
Output
14.31818 MHz Buffered reference clock output.
14
GND
Power
Connect to ground.
15
ASEL
Input
ACLK select pin. Determines frequency of Audio clock per table above.
16
VDD
Power
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
17
PCLK3
Output
PCLK output number 3 per table above.
18
PCLK2
Output
PCLK output number 2 per table above.
19
PSEL0
Input
Processor select pin #0. Determines frequencies on PCLKs 1-4 per table
above.
20
PSEL1
Input
Processor select pin #1. Determines frequencies on PCLKs 1-4 per table
above.
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICS650-01
System Peripheral Clock Source
TSD
IDT / ICS System Peripheral Clock Source
ICS650-01
3
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| ICS670M-01ILFT | 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS650R01I | 制造商:ICS 制造商全称:ICS 功能描述:System Peripheral Clock Source |
| ICS650R-01I | 功能描述:IC CLK SYNTHESIZER 20-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
| ICS650R-01ILF | 功能描述:IC CLK SYNTHESIZER 20-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS650R-01ILFT | 功能描述:IC CLK SYNTHESIZER 20-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| ICS650R-01IT | 功能描述:IC CLK SYNTHESIZER 20-SSOP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器，零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG |
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