参数资料
型号: ICS651G-03T
元件分类: 时钟产生/分配
英文描述: 80 MHz, OTHER CLOCK GENERATOR, PDSO16
封装: 0.173 INCH, TSSOP-16
文件页数: 3/7页
文件大小: 152K
代理商: ICS651G-03T
VOIP Clock Source
MDS 651-03 A
3
Revision 112603
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201www.icst.com
ICS651-03
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS651-03 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(CL -6 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01F decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) Place the 33
series termination resistor (if needed)
close to the clock output to minimize EMI.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS651-03. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
相关PDF资料
PDF描述
ICS662M-03TR 662 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS662M-03LF 662 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS663MILF 663 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
ICS664G-01LFT 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16
ICS664G-01T 74.25 MHz, VIDEO CLOCK GENERATOR, PDSO16
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