参数资料
型号: ICS660GILF
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/7页
文件大小: 0K
描述: IC VIDEO CLK SOURCE DGTL 16TSSOP
标准包装: 96
类型: 时钟发生器
应用: 数字视频
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
产品目录页面: 1252 (CN2011-ZH PDF)
其它名称: 660GILF
800-1088
800-1088-5
800-1088-ND
ICS660
DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
IDT / ICS DIGITAL VIDEO CLOCK SOURCE
2
ICS660
REV G 051310
Pin Assignment
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
Output Clock Selection Table
Pin Descriptions
12
1
11
2
10
X1/REFIN
X2
3
9
VDD
4
VDD
REF
5
S0
6
VDDR
7
GND
8
GND
SELIN
VDDO
S3
S1
S2
CLK
16
15
14
13
S3
S2
S1
S0
Input
Frequency
(MHz)
Output
Frequency
(MHz)
0000
13.5
74.25
0001
13.5
74.175824
0010
27
74.25
0011
27
74.175824
0100
Pass thru
Input Freq
0101
74.25
74.175824
0110
74.175824
74.25
0111
Power down
1000
16.9344
27
1001
125
106.25
1010
14.3181818
27
1011
106.25
125
1100
27.027
27
1101
27
27.027
1110
27
14.3181818
1111
27
17.734472051
1 - 0.16 ppm compared to PAL specification
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X1/REFIN
Input
Connect this pin to a crystal or clock input
2
VDD
Power
Power supply for crystal oscillator.
3
VDD
Power
Power supply for PLL.
4
S0
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
5
GND
Power
Ground for output stage.
6
GND
Power
Ground for PLL.
7
S3
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
8
S2
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
9
CLK
Output
Clock output.
10
S1
Input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
11
VDDO
Power
Power supply for output stage.
12
SEL
Input
Low for clock input, high for crystal. On chip pull-up.
13
GND
Power
Connect to ground.
14
VDDR
Power
Power supply for reference output. Ground to turn off REF.
15
REF
Output
Reference clock output.
16
X2
Input
Connect this pin to a crystal. Leave open if using a clock input.
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