参数资料
型号: ICS667M-01LF
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 74.17582418 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件页数: 2/6页
文件大小: 214K
代理商: ICS667M-01LF
HDTV CLOCK SYNTHESIZER
MDS 667-01 C
2
Revision 031605
I n tegr at ed Circuit Sy stems
525 Race Street , San Jose, CA 95126
t e l (40 8 ) 297-1201
www. i cst.com
ICS667-01
Pin Assignment
Pin Descriptions
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the
ICS667-01 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 2 and 3. It must be
connected close to the ICS667-01 to minimize lead
inductance. Pin 5 can be connected to pin 3. No
external power supply filtering is required for the
ICS667-01.
Series Termination Resistor
A 33
terminating resistor can be used next to the
clock outputs for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 18 pF. A
parallel resonant, fundamental mode, AT cut 27 MHz
crystal should be used. The device crystal connections
should include pads for small capacitors from X1 to
ground and from X2 to ground. These capacitors are
used to adjust the stray capacitance of the board to
match the nominally required crystal load capacitance.
Because load capacitance can only be increased in this
trimming process, it is important to keep stray
capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device.
Crystal capacitors, if needed, must be connected from
each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(CL -16 pF)*2. In this equation, CL= crystal load
capacitance in pF. Example: For a crystal with an 18 pF
load capacitance, each crystal capacitor would be 4 pF
[(18-16) x 2] = 4.
ICLK/X1
VDD
GND
27M
CLK
OE
GND
X2
1
2
3
4
8
7
6
5
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK/X1
XI
Crystal connection. Connect to a 27 MHz fundamental crystal or clock.
2
VDD
Power
Connect to +3.3 V.
3
GND
Power
Connect to ground.
4
CLK
Output
74.17582418 MHz.
5
GND
Power
Connect to ground.
6
OE
Input
Output enable. Tri-states CLK output when low. Internal pull-up to VDD.
7
27M
Output
27 MHz buffered clock or crystal oscillator output.
8
X2
XO
Crystal connection. Connect to a 27 MHz crystal, or leave unconnected
for clock input.
ICS667-01
HDTV CLOCK SYNTHESIZER
TSD
IDT / ICS HDTV CLOCK SYNTHESIZER
ICS667-01
2
相关PDF资料
PDF描述
ICS670M-01I 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS670M-01ILF 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS670M-02 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS670M-03ILFT 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
ICS670M-03ILF 670 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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