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参数资料
| 型号： | ICS726TT |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 36 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封装： | TSOT-23, 6 PIN |
| 文件页数： | 3/6页 |
| 文件大小： | 118K |
| 代理商： | ICS726TT |
12 TO 36 MHZ SOT-23 VCXO
MDS 726 F
3
Revision 112905
In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 297-1 201 ● www.icst.com
ICS726
External Component Selection
The ICS726 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pin 4) and GND (pin 2), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 3) and the load is over 1 inch, series termination
should be used. To series terminate a 50
trace (a
commonly used trace impedance) place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Quartz Crystal
The ICS726 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The ICS726 incorporates on-chip
variable load capacitors that “pull” (change) the
frequency of the crystal. The crystal specified for use
with the ICS726 is designed to have zero frequency
error when the total of on-chip + stray capacitance is 14
pF.
Required Crystal Parameters:
Nominal Frequency
as required MHz
Initial Accuracy at 25°C
-20 min/+20 max ppm
Temperature Stability
-30 min/+30 max ppm
Aging, 1st year
-5 min/+5 max ppm
Aging, 10 years
-20 min/+20 max ppm
Operating Temp. Range, °C
0 min/+25 typ/+70 max
or
Operating Temp. Range, °C
-40 min/+25 typ/+85 max
Load Capacitance
10 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
270 Max
Equivalent Series Resistance
35
Max
The third overtone mode of the crystal and all spurs
must be >100 ppm distant from the 3x fundamental
resonance measured with a physical load of 10 pF.
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS726. There should be no vias between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal. See application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these
capacitors can be found in application note MAN05.
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