参数资料
型号: ICS813001AGILFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 640 MHz, OTHER CLOCK GENERATOR, PDSO24
封装: 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24
文件页数: 2/19页
文件大小: 456K
代理商: ICS813001AGILFT
813001AGI
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 2, 2005
10
Integrated
Circuit
Systems, Inc.
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK PLL
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a
V
w
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LV
C
V
0
=5
1F
p
C
H
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HV
C
V
3
.
3
=4
.
7
2F
p
TABLE 7.VARACTOR PARAMETERS
FORMULAS
(
) (
)
() (
)
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
V
S
L
Low
C
_
2
_
1
_
2
_
1
+
+
=
(
) (
)
() (
)
High
V
S
L
High
V
S
L
High
V
S
L
High
V
S
L
High
C
_
2
_
1
_
2
_
1
+
+
=
6
0
1
0
1
0
10
1
2
1
2
1
)
(
+
+
=
C
TPR
Range
Pull
Total
High
Low
C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were
some assumptions made. First, the stray capacitance (C
S1,
C
S2), which is all the excess capacitance due to board
parasitic, is 4pF. Second, the expected lifetime of the project
is 5 years; hence the inaccuracy due to aging is ±15ppm.
Third, though many boards will not require load tuning
capacitors (C
L1, CL2), it is recommended for long-term
consistent performance of the system that two tuning
capacitor pads be placed into every design. Typical values
for the load tuning capacitors will range from 0 to 4pF.
TPR = ±106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm
The example above will ensure a total pull range of
±106 ppm with an APR of ±51ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to
achieve the required pullability.
C
Low =
(0 + 4p + 15p ) (0 + 4p + 15p )
= 9.5p
C
High =
(0 + 4p + 27.4p ) (0 + 4p + 27.4p )
= 15.7p
1
1
2 220
(1 + 9.5p
4p )
2 220
(1 +15.7p
4p )
1
TPR =
= 106 = 212ppm
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK PLL
TSD
IDT / ICS DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK PLL
ICS813001I
10
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