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参数资料
| 型号： | ICS83052AGILF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 编、解码器及复用、解复用 |
| 英文描述： | 83052 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| 封装： | 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8 |
| 文件页数： | 12/14页 |
| 文件大小： | 1846K |
| 代理商： | ICS83052AGILF |
IDT / ICS 2:1, SINGLE-ENDED MULTIPLEXER
7
ICS83052AGI REV B AUGUST 7, 2006
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
ADDITIVE PHASE JITTER
Additive Phase Jitter (Random)
at 155.52MHz (12kHz - 20MHz)
= 0.18ps (typical)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
than the noise floor of the device. This is illustrated above. The
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source
and measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
1k
10k
100k
1M
10M
100M
相关PDF资料 |
PDF描述 |
|---|---|
| ICS83052AGIT | 83052 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| ICS83054AGI-01 | 83054 SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| ICS83054AGI-01LFT | 83054 SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| ICS83054AGIT | 83054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
| ICS83054AGI | 83054 SERIES, 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS83052AGILFT | 功能描述:IC CLOCK MUX 2:1 250MHZ 8-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS83052AGIT | 制造商:ICS 制造商全称:ICS 功能描述:2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83052I | 制造商:ICS 制造商全称:ICS 功能描述:2:1, SINGLE-ENDED MULTIPLEXER |
| ICS83052I-01 | 制造商:ICS 制造商全称:ICS 功能描述:2-BIT, 2 : 1, SINGLE-ENDED MULTIPLEXER |
| ICS83054AGI | 制造商:ICS 制造商全称:ICS 功能描述:4 : 1, SINGLE-ENDED MULTIPLEXER |
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