参数资料
型号: ICS83058AGILF
厂商: IDT, Integrated Device Technology Inc
文件页数: 12/14页
文件大小: 0K
描述: IC CLOCK MUX 8:1 250MHZ 16-TSSOP
标准包装: 96
系列: HiPerClockS™
类型: 多路复用器
电路数: 1
比率 - 输入:输出: 8:1
差分 - 输入:输出: 无/无
输入: LVCMOS,LVTTL
输出: LVCMOS,LVTTL
频率 - 最大: 250MHz
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
其它名称: 800-1109
800-1109-5
800-1109-ND
83058AGILF
IDT / ICS 8:1, SINGLE-ENDED MULTIPLEXER
7
ICS83058AGI REV. C MARCH 10, 2008
ICS83058I
8:1, SINGLE-ENDED MULTIPLEXER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
As with most timing specifications, phase noise measurements
has issues relatings to the limitations of the equipment. Often
the noise floor of the equipment is higher than the noise floor of
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
the device. This is illustrated above. The device meets the noise
floor of what is shown, but can actually be lower. The phase noise
is dependent on the input source and measurement equipment.
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.19ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
SSB
P
HASE
N
OISE
dB
c
/H
Z
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