参数资料
型号: ICS8305AG
元件分类: 时钟及定时
英文描述: 8305 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封装: 4.40 X 3 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
文件页数: 1/17页
文件大小: 311K
代理商: ICS8305AG
Integrated
Circuit
Systems, Inc.
8305AG
www.icst.com/products/hiperclocks.html
REV. C NOVEMBER 17, 2005
1
ICS8305
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8305 is a low skew, 1-to-4, Differential/
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and
a member of the HiPerClockS family of High
Performance Clock Solutions from ICS. The
ICS8305 has selectable clock inputs that
accept either differential or single ended input levels. The
clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous assertion/
deassertion of the clock enable pin. Outputs are forced LOW
when the clock is disabled. A separate output enable pin
controls whether the outputs are in the active or high imped-
ance state.
Guaranteed output and part-to-part skew characteristics
make the ICS8305 ideal for those applications demanding
well defined performance and repeatability.
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
ICS8305
16-Lead TSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
FEATURES
Four LVCMOS/LVTTL outputs
Selectable differential or LVCMOS/LVTTL clock inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
Maximum output frequency: 350MHz
Output skew: 35ps (maximum)
Part-to-part skew: 700ps (maximum)
Additive phase jitter, RMS: 0.04ps (typical)
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
3.3V/1.5V
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS complaint
packages
LVCMOS_CLK
CLK
nCLK
CLK_SEL
Q0
Q1
Q2
Q3
0
1
CLK_EN
OE
D
Q
LE
0
1
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相关代理商/技术参数
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