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| 型号： | ICS8308AGILFT |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:8 24-TSSOP |
| 标准包装： | 2,500 |
| 系列： | HiPerClockS™ |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:8 |
| 差分 - 输入:输出： | 是/无 |
| 输入： | HCSL，LVCMOS，LVDS，LVHSTL，LVPECL，LVTTL，SSTL |
| 输出： | LVCMOS，LVTTL |
| 频率 - 最大： | 350MHz |
| 电源电压： | 2.375 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 8308AGILFT |
ICS8308AGI REVISION C APRIL 4, 2013
10
2013 Integrated DeviceTechnology, Inc.
ICS8308I Data Sheet
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
APPLICATION INFORMATION
Figure 1 shows how a differential input can be wired to accept
single ended levels.The reference voltage VREF = VDD/2 is generated
by the bias resistors R1 and R2. The bypass capacitor (C1) is
used to help filter noise on the DC bias. This bias circuit should
be located as close to the input pin as possible. The ratio of R1
and R2 might need to be adjusted to position the VREF in the
center of the input voltage swing. For example, if the input clock
swing is 2.5V and VDD = 3.3V, R1 and R2 value should be adjusted
to set VREF at 1.25V. The values below are for when both the single-
ended swing and VDD are at the same voltage. This configuration
requires that the sum of the output impedance of the driver (Ro)
and the series resistance (Rs) equals the transmission line
impedance. In addition, matched termination at the input will
attenuate the signal in half. This can be done in one of two ways.
First, R3 and R4 in parallel should equal the transmission line
FIGURE 1. RECOMMENDED SCHEMATIC FOR WIRING A DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
impedance. For most 50 applications, R3 and R4 can be 100
Ω.
The values of the resistors can be increased to reduce the loading
for slower and weaker LVCMOS driver. When using single ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however V
IL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some of
the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8308AGIT | 制造商:ICS 制造商全称:ICS 功能描述:Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer |
| ICS8308I | 制造商:ICS 制造商全称:ICS 功能描述:Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer |
| ICS830S21AMI-01LF | 功能描述:IC CLK BUFF DRIVER TRANSLA 8SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS830S21AMI-01LFT | 功能描述:IC CLK BUFF DRIVER TRANSLA 8SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS830S21AMILF | 功能描述:IC CLK BUFFER DVR TRANSLA 8-SOIC RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
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