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| 型号： | ICS83948AYI-147LF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 83948 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, LQFP-32 |
| 文件页数： | 13/16页 |
| 文件大小： | 744K |
| 代理商： | ICS83948AYI-147LF |
ICS83948I-147
LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
IDT / ICS LVCMOS/LVTTL CLOCK GENERATOR
6
ICS83948AYI-147 REV. C JANUARY 15, 2008
Table 5B. AC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay
CLK/nCLK; NOTE 1
≤ 350MHz
1.5
4.2
ns
LVCMOS_CLK;
NOTE 2
≤ 350MHz
1.7
4.4
ns
tjit
Buffer Additive Phase Jitter, RMS; refer to
Additive Phase Jitter Section
155.52MHz,
Integration Range:
12kHz – 20MHz
0.14
1
ps
tsk(o)
Output Skew; NOTE 3, 7
Measured on the Rising Edge
@ VDDO/2
160
ps
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
Measured on the Rising Edge
@ VDDO/2
2ns
tR / tF
Output Rise/Fall Time
0.6V to 1.8V
0.1
1.0
ns
odc
Output Duty Cycle
≤ 150MHz, Ref = CLK/nCLK
40
60
%
tPZL, tPZH
Output Enable Time; NOTE 5
5ns
tPLZ, tPHZ
Output Disable Time; NOTE 5
5ns
tS
Clock Enable
Setup Time;
NOTE 6
CLK_EN to CLK/nCLK
1
ns
CLK_EN to
LVCMOS_CLK
0ns
tH
Clock Enable
Hold Time;
NOTE 6
CLK/nCLK to CLK_EN
0
ns
LVCMOS_CLK to
CLK_EN
1ns
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| ICS83948AYI-147LFT | 83948 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
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相关代理商/技术参数 |
参数描述 |
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| ICS83948AYI-147LFT | 功能描述:IC CLOCK BUFFER MUX 2:12 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS83948AYI-147T | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS83948AYIL | 制造商:ICS 制造商全称:ICS 功能描述:LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| ICS83948AYILF | 功能描述:IC CLOCK BUFFER MUX 2:12 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
| ICS83948AYILFT | 功能描述:IC CLOCK BUFFER MUX 2:12 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器，驱动器 系列:HiPerClockS™ 标准包装:74 系列:- 类型:扇出缓冲器（分配） 电路数:1 比率 - 输入:输出:1:10 差分 - 输入:输出:是/是 输入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 输出:HCSL，LVDS 频率 - 最大:400MHz 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:管件 |
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