参数资料
型号: ICS840002AGI-01LF
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/14页
文件大小: 0K
描述: IC FREQ SYNTHESIZER 16-TSSOP
标准包装: 96
系列: HiPerClockS™, FemtoClock™
类型: 频率合成器
PLL: 带旁路
输入: 晶体
输出: LVCMOS,LVTTL
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 175MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
其它名称: 800-2244
840002AGI-01LF
ICS840002AGI-01LF-ND
ICS840002I-01 Data Sheet
FEMTOCLOCK, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS840002AGI-01 REVISION B FEBRUARY 3, 2011
10
2011 Integrated Device Technology, Inc.
Layout Guideline
Figure 2 shows a schematic example of the ICS840002I-01
application schematic. In this example, the device is operated at VDD
= VDDA = VDDO = 3.3V. The 18pF parallel resonant 25MHz crystal is
used. The load capacitance C1 = 22pF and C2 = 22pF are
recommended for frequency accuracy. Depending on the parasitic of
the printed circuit board layout, these values might require a slight
adjustment to optimize the frequency accuracy. Crystals with other
load capacitance specifications can be used. This will required
adjusting C1 and C2.
As with any high speed analog circuitry, the power supply pins are
vulnerable to noise. To achieve optimum jitter performance, power
supply isolation is required. The ICS840002I-01 provides separate
power supplies to isolate from coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1uF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequencies.
This low-pass filter starts to attenuate noise at approximately 10kHz.
If a specific frequency noise component is known, such as switching
power supply frequencies, it is recommended that component values
be adjusted and if required, additional filtering be added. Additionally,
good general design practices for power plane voltage stability
suggests adding bulk capacitances in the local area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 2. ICS840002I-01 Application Schematic Example
C10
0.1u
BLM18BB221SN2
Ferrite Bead
1
2
C9
10uF
XTAL_OUT
RU2
Not Install
VDDO
Zo = 50 Ohm
Logic Control Input Examples
C5
0.1u
RD1
Not Install
VDD
1 8 p F
R4
100
C3
10uF
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Set Logic
Input to
'1'
VDD
VDDO
Optional Termination
C4
0.1u
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
XTAL_OUT
XTAL_IN
VDDO
Q1
Q0
GND
FSEL1
R3
100
R1
33
To Logic
Input
pins
XTAL_IN
Zo = 50 Ohm
LVCMOS
3.3V
VDD
X1
25MHz
RD2
1K
VDDO
LVCMOS
C8
0.1uF
C2
22pF
BLM18BB221SN1
Ferrite Bead
1
2
3.3V
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
R2
10
C7
0.1uF
RU1
1K
To Logic
Input
pins
VDDA
C1
22pF
VDD
C6
10uF
Set Logic
Input to
'0'
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