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参数资料
| 型号： | ICS840004AG-01LFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 175 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封装： | 6.50 X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件页数： | 14/14页 |
| 文件大小： | 418K |
| 代理商： | ICS840004AG-01LFT |
Integrated
Circuit
Systems, Inc.
840004AG-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 28, 2006
9
ICS840004-01
FEMTOCLOCKSCRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
NPUTS
:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
Figure 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50
Ω applications, R1 and R2 can be
100
Ω. This can also be accomplished by removing R1 and
making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
ICS840004-01
FEMTOCLOCKS CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TSD
IDT / ICS FEMTOCLOCKS CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS840004-01
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS840004AG-01T | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| ICS840004AG-11 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| ICS840004AG-11LF | 功能描述:IC FREQ SYNTHESIZER 20-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS840004AG-11LFT | 功能描述:IC FREQ SYNTHESIZER 20-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
| ICS840004AG-11T | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
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