参数资料
型号: ICS8427DK-02T
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟产生/分配
英文描述: 500 MHz, OTHER CLOCK GENERATOR, QCC32
封装: 5 X 5 MM, 0.75 MM HEIGHT, MO-220VHHD-2, VFQFN-32
文件页数: 17/23页
文件大小: 1597K
代理商: ICS8427DK-02T
IDT / ICS LVHSTL FREQUENCY SYNTHESIZER
3
ICS8427DY-02 REV A OCTOBER 13, 2006
ICS8427-02
500MHZ, LOW JITTER, LVCMOS/CRYSSTAL-TO-LVHSTL FREQUENCY SYNTHESIZER
t
S
t
H
t
S
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
T1
T0
N2
N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0 SSC
Time
M AND N DIVIDERS, SSC AND TEST MODE CONTROL BITS
1
T0
T2
N1
N0
N8
M7
M6
M5
M4
M3
M2
M1
M0
MC
S
Test Mode
Control Register
N Divider
M Divider
SSC Control
Register
S_DATA
TEST Output
T1:T0 = 01
Shift Register
Data transfer from shift register
to M and N dividers and SSC and Test
Control Bits on a low-to-high transi-
tion of S_LOAD.
1
T0
T2
N1
N0
N8
M7
M6
M5
M4
M3
M2
M1
M0
MC
S
ICS8427-02 SHIFT REGISTER OPERATION – READ BACK CAPABILITY
1. Device powers up by default in Test Mode 01.
The Test Output in this case is wired to the shift register.
2. Shift in serial data stream and latch into M, N, T1, T0 and SSC Control Bits.
Shift in T1:T0=00, so that the TEST Output will be turned off after the bits are shifted in and latched.
Data transferred to M, N dividers, TEST and SSC Control Bits.
Changes to M, N, SSC and TEST mode bits take affect at this time.
Data latched into M, N Dividers, TEST and SSC control bits.
TEST Output
S_CLOCK
S_DATA
S_LOAD
TABLE 1. SSC FUNCTION TABLE
C
S
Se
t
a
t
S
C
S
0)
t
l
u
a
f
e
d
p
u
-
r
e
w
o
p
(
f
O
1d
a
e
r
p
s
-
n
w
o
d
%
5
.
0
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