参数资料
型号: ICS843001CGILFT
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/7页
文件大小: 0K
描述: IC CLK GEN FIBRE CH 8TSSOP
标准包装: 2,500
系列: HiPerClockS™, FemtoClock™
类型: 频率合成器
PLL:
输入: 晶体
输出: LVPECL
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 无/是
频率 - 最大: 212.5MHz
除法器/乘法器: 是/无
电源电压: 2.375 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 带卷 (TR)
4
Precision Edge
SY89321L
Micrel, Inc.
M9999-060208
hbwhelp@micrel.com or (408) 955-1690
V
CC = +3.3V ±10%; CL = 20pF, TA = –40°C to +85°C unless otherwise noted.
Symbol
Parameter
Condition
Min
Typ
Max
Units
f
MAX
Maximum Input Frequency
Note 6
275
——
MHz
tpd
Propagation Delay
1.5
1.9
2.5
ns
t
skpp
Part-to-Part Skew
V
IN ≥ 100mV, Note 7
——
0.5
ns
V
CMR
Common Mode Range
1.2
V
CC
V
PP
Minimum Peak-to-Peak Input
Note 8
100
——
mV
t
r
Output Rise/Fall Time
0.5
1.0
ns
t
f
(1.0V to 2.0V)
t
JITTER
Cycle-to-cycle (rms)
Note 9
2ps
RMS
Total jitter (pk-pk)
Note 10
15
ps
PP
Note 6.
The f
MAX value is specified as the minimum guaranteed maximum frequency (While maintaining TTL swing of 0.8V to 2.0V). Actual opera-
tional maximum frequency may be greater.
Note 7.
Part-to-Part Skew considering HIGH-to-HIGH transitions at common V
CC level.
Note 8.
V
PP(min) is the minimum input swing for which AC parameters are guaranteed.
Note 9.
Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, T
n – Tn–1,where T is the time between rising edges of the
output signal.
Note 10. Total jitter definition: with an ideal clock input of frequency
≤ f
MAX, no more than one output edge in 10
12 output edge will deviate by more than
the specified peak-to-peak jitter value.
AC ELECTRICAL CHARACTERISTICS
INPUT INTERFACE APPLICATIONS
IN
VCC
/IN
SY89321L
VBB
0.01
F
Single-Ended Input
(Terminating unused input)
IN
3.3V
/IN
SY89321L
100
CML
CML Input
IN
V
CC
/IN
SY89321L
100
LVDS
LVDS Input
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