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参数资料
| 型号： | ICS843002CY-31T |
| 厂商： | SPECTRUM CONTROL INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封装： | 10 X 10 MM, 1 MM HEIGHT, EXPOSED PAD, MS-026BCD, TQFP-64 |
| 文件页数： | 24/27页 |
| 文件大小： | 270K |
| 代理商： | ICS843002CY-31T |
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 22, 2005
6
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PRELIMINARY
SECTION 1. FREQUENCY TRANSLATION
The ICS843002-31 is a two stage device, a VCXO PLL stage
followed by a low phase noise FemtoClock multiplier stage.
The VCXO uses a pullable crystal to lock to the reference
clock and can provide an output frequency up to 25MHz on
the single-ended VCLK output. For higher frequencies, the low
phase noise FemtoClock can multiply the VCXO PLL out-
put clock up to 700MHz on 2 differential LVPECL output
pairs (QA/nQA, QB/nQB).
The VCXO PLL stage has a 13-bit input divider and a 13-bit
feedback divider to generate large integer ratios needed for
some frequency translation applications. When configuring
the device is to use pullable crystals in the 17.5MHz – 25MHz
range on the VCXO PLL stage, and ensure that the
FemtoClock PLL is kept within its range of 560MHz to 700MHz.
Below are 3 examples:
1. 8kHz to 622.08MHz and 155.52MHz
This frequency translation requires use of both the VCXO
PLL and the FemtoClock circuit. The VCXO PLL can be used
to multiply up to 19.44MHz for use as a reference clock for
the FemtoClock which will do the multiplication from
19.44MHz to 622.08MHz.
Using a 19.44MHz pullable crystal on XTAL_IN/
XTAL_OUT, set the VCXO PLL feedback divider pins,
XOFB[12:0], to 2430. This multiplies the 8kHz refer-
ence clock to 19.44MHz.
Set the FemtoClock multiplication control pin, MP, to
0 which sets the multiplication factor to 32. This sets
the FemtoClock VCO to 622.08MHz.
Set the QA/nQA output divider control pins,
NPA[2:0] = 000 for divide by 1. This sets the QA/nQA
LVPECL output pair for 622.08MHz.
Set the QB/nQB output divider control pins,
NPB[2:0] = 010 for divide by 4. This sets the QB/nQB
LVPECL output pair for 155.52MHz.
2. T1 to T3. (1.544MHz to two 44.736MHz outputs)
Since 44.736MHz is slightly higher than the maximum VCXO
output frequency, the FemtoClock circuit will have to be used.
Using a pullable 22.368MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 2796 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 22.368MHz
(1.544MHz * 2796/193 = 22.368MHz).
Set the FemtoClock multiplication control pin, MP, to
28 which sets the VCO at 626.304MHz.
Set the QA/nQA output divider control pins,
NPA[2:0] = 101 for divide by 14. This sets the QA/nQA
LVPECL output pair for 44.736MHz.
Set the QB/nQB output divider control pins,
NPB[2:0] = 000 for divide by 1. This sets the QB/nQB
LVPECL output pair for 44.736MHz
3. T1 to E1. (1.544MHz to two 2.048MHz outputs)
The 2.048MHz output frequency requirement is low enough
that the FemtoClock circuit is not required. Only the VCXO
stage is used for this frequency translation.
Using a pullable 24.576MHz on XTAL_IN/XTAL_OUT,
set the VCXO PLL feedback divider pins, XOFB[12:0]
to 3072 and the input divider pins, XOIN[12:0] to 193.
This multiplies the 1.544MHz reference to 2.048MHz
(1.544MHz * 3072/193 = 24.576MHz).
Set the VCXO PLL Output Divider control pins,
NV[1:0] = 01 for /12.This divides the 24.576MHz VCXO
PLL frequency down to 2.048MHz.
The Frequency Configuration Table Examples (see the follow-
ing pages) are intended to show the most common frequency
translation requirements. It is sorted in order of descending
input frequency. It is not intended to be an exhaustive configur-
ation table because that would be impractical with almost 3
billion possible configurations. As far as configuration is
concerned, frequencies <= 25MHz can be generated with the
VCXO PLL while frequencies > 25MHz require the use of the
downstream FemtoClock which can multiply the VCXO PLL
output up to 700MHz. Complex integer ratios are handled with
the VCXO PLL stage and the FemtoClock circuit can be
configured to multiply the VCXO PLL output by 32 or 28. The
following example will illustrate the configuration process.
Assume you have a 1.544MHz T1 clock which needs to be
multiplied up to 622.08MHz (OC12). Obviously, the
FemtoClock multiplier will be needed to achieve 622.08MHz.
Since the FemtoClock has a selectable multiplication factor
of 28 or 32, this means there are 2 viable VCXO PLL crystal
choices which fall within its 17.5MHz – 15MHz range:
22.217143MHz (/28 feedback divider) or 19.44MHz (/32
feedback divider). Use of the /28 feedback divider for the
FemtoClock multiplier will give slightly better phase noise,
but in this case 22.217143/1.544 cannot be exactly
achieved with the 13-bit input and feedback VCXO PLL
dividers. Using the x32 setting of the FemtoClock allows a
ratio of 19.44/1.544 = 2430/193 which is easily achievable.
So the FemtoClock would be set for x32 and a 19.44MHz
crystal would be used. The VCXO PLL input divider would
be set for 193 and the VCXO PLL feedback divider would
be set for 2430. To double check the solution, perform the
following calculation: 1.544 * 2430 * 32/193 = 622.08MHz.
The 2nd FemtoClock multiplier output, QB/nQB, can be set to
equal the QA/nQA output frequency or a fraction of its frequency.
The following fractional values are available: /1, /2, /4, /8.
SECTION 2. FREQUENCY CONFIGURATION
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| ICS843004AG-02LFT | 637.5 MHz, OTHER CLOCK GENERATOR, PDSO24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS843002I | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-01 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-40 | 制造商:ICS 制造商全称:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-41 | 制造商:ICS 制造商全称:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-72 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ VCXO BASED WCDMA CLOCK GENERATOR/JITTER ATTENUATOR |
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