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参数资料
| 型号： | ICS843034AYT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 750 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 |
| 文件页数： | 18/24页 |
| 文件大小： | 726K |
| 代理商： | ICS843034AYT |
IDT / ICS 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
3
ICS843034AY REV B JULY 18, 2006
ICS843034
FEMTOCOCKS MULTI-RATE 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
specific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel input
mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B to program the VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 23
≤ M ≤ 30. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and Nx output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and Nx output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and Nx output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and Nx bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS843034 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscil-
lator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference
frequency. The VCO of the PLL operates over a range of 560MHz
to 750MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M,
NA, and NB inputs are passed directly to the M divider and
both N output dividers. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M and N dividers
remain loaded until the next LOW transition on nP_LOAD or
until a serial event occurs. As a result, the M and Nx bits can
be hardwired to set the M divider and Nx output divider to a
T1
T0
TEST Output
00
LOW
0
1
S_Data, Shift Register Output
1
0
Output of M divider
1
FOUTA0 same frequency
fVCO = fxtal x M
FOUT = fVCO = fxtal x M
N
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T 1
T0
NB2
NB1
NB0
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, NA0:NA2, NB0:NB2
nP_LOAD
S_LOAD
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
S
t
H
t
S
t
H
Time
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相关代理商/技术参数 |
参数描述 |
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| ICS843051 | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS8430-51 | 制造商:ICS 制造商全称:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS843051AG | 制造商:ICS 制造商全称:ICS 功能描述:FEMTOCLOCKS CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| ICS843051AGLF | 功能描述:IC CLK GEN GIG ETH LVPECL 8TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS843051AGLFT | 功能描述:IC CLOCK GENERATOR LVPECL 8TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™, FemtoClock™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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