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| 型号： | ICS8430AY-111LF |
| 元件分类： | 时钟及定时 |
| 英文描述： | PLL BASED CLOCK DRIVER, PQFP32 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026, LQFP-32 |
| 文件页数： | 2/8页 |
| 文件大小： | 105K |
| 代理商： | ICS8430AY-111LF |
8430-111
www.icst.com
REV. A FEBRUARY 15, 2001
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8430-111
700MHZ, LOW JITTER
LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS8430-111 features a fully integrated PLL and therefore requires no external component to for setting the loop
bandwidth. A differential clock input is used as the input to the ICS8430-111. This input is divided by 16 prior to the
phase detector. A16MHz clock input provides a 1MHz reference frequency. The VCO of the PLL operates over a range
of 250 to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The output of
the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the ICS8430-111 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In
parallel mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to
the ripple counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired
to set the ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW
when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the loop
divider is defined as follows:
The M count and the required values of M0 through M8 are shown in
Table 4B, Programmable VCO Frequency Function Table.
The frequency out is defined as follows:
Note that the factor of 2 in the preceding equations is a result of the additional
÷2 that is placed in the feedback prior to the ÷M.
Serial operation occurs when nP_LOAD and S_LOAD are HIGH and the shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift register are passed to the ripple counter when S_LOAD transitions
from HIGH-to-LOW. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers
T0 and T1 determine the state of the TEST output as follows:
fVCO = fIN x 2M
16
T1
T0
TEST Output
0
LOW
0
1
S_Data clocked into register
1
0
Output of M divider
1
CMOS Fout
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
T1
T0
N 2
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N2
nP_LOAD
N
fOUT = fVCO = fIN x 2M
N
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ICS8430AY-51 | 制造商:ICS 制造商全称:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AY-51T | 制造商:ICS 制造商全称:ICS 功能描述:600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8430AY-61 | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS8430AY-61LF | 功能描述:IC SYNTHESIZR DUAL LVPECL 32LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ICS8430AY-61LFT | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:HiPerClockS™ 标准包装:1,000 系列:- 类型:时钟/频率合成器，扇出分配 PLL:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 除法器/乘法器:- 电源电压:- 工作温度:- 安装类型:表面贴装 封装/外壳:56-VFQFN 裸露焊盘 供应商设备封装:56-VFQFP-EP（8x8） 包装:带卷 (TR) 其它名称:844S012AKI-01LFT |
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